DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 and 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakatogawa (US 20200051495) in view of Patel(US 20160269720).
As to claims 1 and 14, Nakatogawa(US 20200051495) teaches a display apparatus, comprising: a first display module(10), comprising a first substrate(60)(see Figs. 1-2; [0026]), wherein N first signal lines(140, a natural number more than 2)(see Figs. 1, 3 and [0005, 0033]) and a multiplexer(160) are arranged on the first substrate(60)(see Figs. 1-3; [0032-0033]); a second display module(20), comprising a second substrate(60), wherein N second signal lines(230, a natural number more than 2)(see Figs. 1-3 and [0005, 0038]); and a first demultiplexer(250) are arranged on the second substrate(60)(see Figs. 1-3 and [0032, 0038]); and a first flexible circuit board(50)(see Figs. 1, 3 [0026]), wherein a first connection end of the first flexible circuit board is fixed to the first substrate(60)(see Figs. 1, 3; [0026, 0031]), the multiplexer(160) is electrically connected between a first connection end part(30) and the first signal lines(140); a second connection end of the first flexible circuit board(50) is fixed to the second substrate(60)(see Figs. 1-3 and [0026, 0031]), and the first demultiplexer(250) is electrically connected between the second connection end of the connection part(30) and the second signal lines(230)(see Figs. 1-3; [0038]), wherein a number of electrical connection lines in the first flexible circuit board is M(natural number), M is less than N, and both of M and N are positive integers(see Fig. 3 and [0031]).
Nakatogawa fails to disclose a first flexible circuit board located between the first and second display panel.
Patel(US 20160269720) teach a display apparatus comprising a first flexible circuit board(Integrated circuits or chips) located between a first display(102-a) and a second display(102(b)(see Fig. 4B; [0034]). At the time of effective filing date, it would have been obvious to one of ordinary skill to have modified Nakatogawa with the teaching Patel, since a circuit board could be changed, it would not have modified the operation the circuit board and it was a design choice(see MPEP 2144.04). Changing location a circuit board has been disclosed by Patel(see Figs. 4A-4B; [0033, 0034]).
As to claims 2 and 15, Nakatogawa, further, discloses both of the first signal lines (Fig. 3, (140) and the second signal lines (Fig. 3,(230) comprise data lines [0037-0038].
As to claims 3 and 16, Nakatogawa, further, discloses the multiplexer (Fig. 3, (160) comprises at least one multiplexing unit (Fig. 5, (160(1)[0043], and the multiplexing unit comprises P first input ends (Fig. 5, (162(1), (162(2) and (162(3)) [0044]and one first output end (Fig. 5, (310(1))[0044]; the first demultiplexer (Fig. 5, (250) [0046] comprises at least one first demultiplexing unit (Fig. 5, (250(1), and the first demultiplexing unit comprises one second input end (310(1) and P second output ends (Fig. 5, (252(1), (252(2), and (252(3))[0046]; P is an integer, and 1 <P<N [0044, 0046]; the multiplexing units are in one-to-one correspondence with the first demultiplexing units [0044, 0046]; and each of the first input ends in the multiplexing unit is in one-to-one correspondence with each of the second output ends in the corresponding first demultiplexing unit [0044, 0046]; a scan duration for each row of pixels comprises P sub-scan periods (Fig. 7, (t1-t7) and Fig. 8, (t1-t29)[0054-0056]; for each of the multiplexing units, in each of the sub-scan periods, only one of the first input ends and its corresponding second output end are electrically conducted [0054 and 0056-0061]; and the first input end that is in an electrically conducted state is different in different sub-scan periods[0054 and 0056-0061].
As to claims 4 and 17, further, Nakatogawa discloses a driver chip (Fig. 3, (40) and timing control traces (Fig. 3, (lines that connect driver chip (40) to the Multiplexer (160) and to the demultiplexer (250); wherein the driver chip is fixed on the first substrate (Fig. 3, (40 and 50) are fixed to substrate (60)), and the driver chip is electrically connected to the first signal lines [0033]; the driver chip is further electrically connected to the multiplexer and the first demultiplexer through the timing control traces (Fig. 3, (lines that connect driver chip (40) to the Multiplexer (160) and to the demultiplexer (250)) , to control the first input end and its corresponding second output end to be electrically conducted [0033, 0035, 0037].
As to claims 5 and 18, Nakatogawa, further, discloses a second demultiplexer (Fig. 12, (850)[0083], wherein the second demultiplexer [00850] is electrically connected between the driver chip and the first signal lines [0079]; the driver chip is further electrically connected to the second demultiplexer through the timing control traces [0083-0085].
As to claims 6 and 19, Nakatogawa, further, discloses the second demultiplexer (Fig. 12, (850)[0083]comprises at least one second demultiplexing unit[0083], and the second demultiplexing unit comprises one third input end (Fig. 12, (910) and P third output ends (Fig. 12, (3 outputs coming out of (850); the multiplexing units (Fig. 12, (190) are in one-to-one correspondence with the second demultiplexing units (850)[0084]; each of the first input ends in the multiplexing unit is in one-to-one correspondence with each of the third output ends in the corresponding second demultiplexing unit; the first input end and its corresponding third output end are electrically connected to the same first signal line; the third input end is electrically connected to the driver chip[0044, 0046]; in each of the sub-scan periods, for each of the second demultiplexing units, the third input end is electrically conducted with only one of the first input ends, and the first input end that is in an electrically conducted state is electrically conducted with its corresponding second output end; and the first input end that is electrically conducted with the third input end is different in different sub-scan periods[0054 and 0056-0061]. Although the details are being omitted, it would have been obvious to one of ordinary skill in the art at the time of filling to have the same correspondence between inputs and outputs of the second demultiplexer and the multiplexer, as it was the case with the first demultiplexer and the multiplexer, since, in a lab, or manufacturing environment, a duplicate effect would obtain the same desired results.
As to claims 7 and 20, Nakatogawa, further, discloses the first substrate (Fig. 3, (60) comprises a first display region (Fig. 3, (102) and a first non-display region surrounding the first display region (Fig. 3, (110, 120)[0034]; the second substrate (Fig. 3, (60) comprises a second display region (Fig. 3, (202) and a second non-display region surrounding the second display region(Fig. 3, (210)[0039]; the first display module (10) and the second display module (20) are arranged side by side (Fig. 3); the driver chip (Fig. 3, (40) and the second demultiplexer (Fig. 12, (850)are located on a side of the first non-display region away from the second display module (Fig. 12), the multiplexer (Fig. 3, (160) is located on a side of the first non-display region (102) close to the second display module (20), the first demultiplexer (Fig. 3, (250) is located on a side of the second non-display region (202) close to the first display module (Fig. 3, (10).
As to claim 8, Nakatogawa, further, does not specifically disclose the first flexible circuit board (Figs. 2A-2C, and 4B, (104) comprises a bending region [0022]; a distance between the first display module (102-a) and the second display module (102-b) is adjustable; and a bending state of the bending region of the first flexible circuit board changes with the distance between the first display module and the second display module.
Patel discloses the first flexible circuit board (Fig. comprises a bending region; a distance between the first display module and the second display module is adjustable (Figs. 2A, 2B, (D1, D2))[0020]; and a bending state of the bending region of the first flexible circuit board changes with the distance between the first display module and the second display module [0020, 0022]. At the time of effective filing date, it would have been obvious to one of ordinary skill to have modified Nakatogawa with the teaching Patel, so that it may be suitable for a second human having a second inter-pupillary distance [0020].
As to claim 9, Nakatogawa, further, does not specifically disclose a first reinforcing layer is arranged on a side of the first connection end of the first flexible circuit board away from the first substrate; and a second reinforcing layer is arranged on a side of the second connection end of the first flexible circuit board away from the second substrate.
Patel, further, discloses a first reinforcing layer [0022]is arranged on a side of the first connection end [0022]of the first flexible circuit board (Fig. 2A, 2B, 2C, (104) away from the first substrate (106-a); and a second reinforcing layer [0022]is arranged on a side of the second connection end [0022]of the first flexible circuit board away from the second substrate (106-b). (“the flexible substrate region 104 may be formed of bands of materials of different bending moduli or elastic moduli, thus making the flexible substrate region 104 more prone (likely) to bend in certain regions (260-b) where the region 104 is softer, less stiff, and more pliable than other regions (260-a) where the flexible substrate 104 is made of stiffer materials.”)[0022] At the time of effective filing date, it would have been obvious to one of ordinary skill to have modified Nakatogawa with the teaching Patel, for making the flexible substrate region 104 more prone (likely) to bend in certain regions where the region is softer, less stiff, and more pliable than other regions where the flexible substrate is made of stiffer materials [0022].
As to claim 10, Nakatogawa, further, does not specifically disclose the first reinforcing layer covers an end of the first connection end and is in contact with the first substrate.
Patel discloses the first reinforcing layer [0022] covers an end of the first connection end [0022] and is in contact with the first substrate(106-a)[0022].(see claim 9)(one of the bands by which the flexible substrate region may be formed is in contact with the first substrate [0022]. At the time of effective filing date, it would have been obvious to one of ordinary skill to have modified Nakatogawa with the teaching Patel, for making the flexible substrate region 104 more prone (likely) to bend in certain regions where the region is softer, less stiff, and more pliable than other regions where the flexible substrate is made of stiffer materials [0022].
As to claim 12, Nakatogawa, further, discloses a second flexible circuit board (Fig. 3, (50) and a printed circuit board (Fig. 12, (90)[0079, 0081]; wherein the driver chip (Fig. 3, (40) is electrically connected to the printed circuit board (Fig. 3, (90) through the second flexible circuit board (Fig. 3, (50); the printed circuit board (50) is located on a non-light-emitting side of the first display module (Fig. 3, (10)(printed circuit board (50) is in a non-display side of first display module (10).
As to claim 13, Nakatogawa, further, discloses the first display module (10) and the second display module (20)are both in a shape of a convex polygon (Fig. 13, (10, 20)).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 11 is indicated as allowable since certain key features of the claimed invention are not taught or fairly suggested by the prior art. In claim 11, “a third reinforcing structure is arranged on a side of the first connection end of the first flexible circuit board close to the first substrate, the third reinforcing structure is located in a step region formed by the first flexible circuit board and the first substrate, and is fixed to a surface of the first connection end of the first flexible circuit board close to the first substrate and a sidewall of the first substrate”. The closest prior art of record, Nakatogawa(US 20200051495) teaches a display apparatus, comprising: a first display module(10), comprising a first substrate(60)(see Figs. 1-2; [0026]), wherein N first signal lines(140, a natural number more than 2)(see Figs. 1, 3 and [0005, 0033]) and a multiplexer(160) are arranged on the first substrate(60)(see Figs. 1-3; [0032-0033]); a second display module(20), comprising a second substrate(60), wherein N second signal lines(230, a natural number more than 2)(see Figs. 1-3 and [0005, 0038]); and a first demultiplexer(250) are arranged on the second substrate(60)(see Figs. 1-3 and [0032, 0038]); and a first flexible circuit board(50)(see Figs. 1, 3 [0026]), wherein a first connection end of the first flexible circuit board is fixed to the first substrate(60)(see Figs. 1, 3; [0026, 0031]), the multiplexer(160) is electrically connected between a first connection end part(30) and the first signal lines(140); a second connection end of the first flexible circuit board(50) is fixed to the second substrate(60)(see Figs. 1-3 and [0026, 0031]), and the first demultiplexer(250) is electrically connected between the second connection end of the connection part(30) and the second signal lines(230)(see Figs. 1-3; [0038]). However, singularly or in combination, fails to anticipate or render the above underlined limitations obvious, together with all the other limitations of the claims.
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/RICARDO OSORIO/
Primary Examiner, Art Unit 2621