Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over Betz (US 2017/0272073 A1) in view of KOSTAS (US 2023/0102185 A1).
In regards to claim 1, Betz teaches:
A dynamic selection method for a data region applied to an integrated circuit device, comprising: acquiring a test dataset and/or simulation dataset corresponding to the integrated circuit device; (Abstract & 0038, The dynamic parameter scaling controller also stores one or more functional values for the operating parameter in a calibration table. The dynamic parameter scaling controller also operates the programmable logic fabric using a design configuration using dynamic values for the operating parameter based at least in part on the one or more operating conditions. Returning to FIG. 1, the integrated circuit 12 also includes IO blocks 60 that may be used to write data to the integrated circuit 12 and/or read data from the integrated circuit 1.) acquiring a plurality of bias condition variables associated with the integrated circuit device according to a user instruction, the bias condition variables being associated with a data item to be tested and/or a data item to be simulated of the integrated circuit device; acquiring bias conditions corresponding to the bias condition variables according to a user instruction; (0006, Present embodiments relate to systems, methods, and devices for dynamically modifying operating parameters (e.g., voltage or frequency) of an FPGA based at least in part on operating conditions (e.g., temperature) of a specific design of the FPGA.) and performing a test operation according to the dynamic test dataset and/or perform a simulation operation according to the dynamic simulation dataset for the integrated circuit device. (0045, FIG. 8 illustrates a detailed flow diagram view of a process 120 for dynamically varying temperature, voltage, and frequency. The FPGA is set to one of a number of calibration configurations to be tested (block 122).)
Betz fails to teach:
generating a customized selection model associated with the data item to be tested and/or the data item to be simulated according to the bias condition variables and the bias conditions; selecting a corresponding dynamic test dataset from the test dataset according to the customized selection model; and/or selecting a corresponding dynamic simulation dataset from the simulation dataset according to the customized selection model;
However, KOSTAS teaches:
generating a customized selection model associated with the data item to be tested and/or the data item to be simulated according to the bias condition variables and the bias conditions; selecting a corresponding dynamic test dataset from the test dataset according to the customized selection model; and/or selecting a corresponding dynamic simulation dataset from the simulation dataset according to the customized selection model; (0040 & 0084, At block 330, a plurality of test case clusters is generated based on a clustering model and the embedding data set. operation that involves inputting an existing dataset (often labeled or tagged), iterating over the dataset, and then adjusting model parameters, such as weights and biases, in order to improve model performance.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of operating a dynamic parameter scaling controller of Betz with the teaching of KOSTAS, which teaches a testing integrated circuit designs based on test cases selected using machine learning models in order to automate integrated chip testing (KOSTAS: 0003, the process of testing an integrated circuit using electronic design automation (EDA) tools may still be a very resource-intensive process.)
In regards to claim 2, Betz in view of KOSTAS teaches:
The dynamic selection method for the data region applied to the integrated circuit device according to claim 1, wherein the bias condition variables comprise a plurality of first feature points of the data item to be tested; and/or a plurality of second feature points of the data item to be simulated. (0006, Present embodiments relate to systems, methods, and devices for dynamically modifying operating parameters (e.g., voltage or frequency) of an FPGA based at least in part on operating conditions (e.g., temperature) of a specific design of the FPGA)
In regards to claim 3, Betz in view of KOSTAS teaches the method of claim 2.
Betz fails to teach:
The dynamic selection method for the data region applied to the integrated circuit device according to claim 2, wherein in the case that the data item to be tested comprises voltages at a plurality of first test points in an integrated circuit associated with the integrated circuit device, the first feature points comprise: a maximum voltage value of the first test point, a minimum voltage value of the first test point, a zero voltage value of the first test point, a saturation voltage value of the first test point, and a valve voltage value of the first test point.
However, KOSTAS teaches:
The dynamic selection method for the data region applied to the integrated circuit device according to claim 2, wherein in the case that the data item to be tested comprises voltages at a plurality of first test points in an integrated circuit associated with the integrated circuit device, the first feature points comprise: a maximum voltage value of the first test point, a minimum voltage value of the first test point, a zero voltage value of the first test point, a saturation voltage value of the first test point, and a valve voltage value of the first test point. (0051, While the voltage parameters in this test case are illustrated as the same minimum and maximum voltages, it should be recognized that any range of voltage parameters may be specified in a test case name.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of operating a dynamic parameter scaling controller of Betz with the teaching of KOSTAS, which teaches a testing integrated circuit designs based on test cases selected using machine learning models in order to automate integrated chip testing (KOSTAS: 0003, the process of testing an integrated circuit using electronic design automation (EDA) tools may still be a very resource-intensive process.)
In regards to claim 4, Betz in view of KOSTAS teaches the method of claim 2.
Betz fails to teach:
The dynamic selection method for the data region applied to the integrated circuit device according to claim 2, wherein in the case that the data item to be simulated comprises voltages at a plurality of second test points in the integrated circuit associated with the integrated circuit device, the second feature points comprise: a maximum voltage value of the second test point, a minimum voltage value of the second test 12 point, a zero voltage value of the second test point, a saturation voltage value of the second test point, and a valve voltage value of the second test point.
However, KOSTAS teaches:
The dynamic selection method for the data region applied to the integrated circuit device according to claim 2, wherein in the case that the data item to be simulated comprises voltages at a plurality of second test points in the integrated circuit associated with the integrated circuit device, the second feature points comprise: a maximum voltage value of the second test point, a minimum voltage value of the second test 12 point, a zero voltage value of the second test point, a saturation voltage value of the second test point, and a valve voltage value of the second test point. (0051 & 0076, While the voltage parameters in this test case are illustrated as the same minimum and maximum voltages, it should be recognized that any range of voltage parameters may be specified in a test case name. a second test case from the plurality of target test cases.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of operating a dynamic parameter scaling controller of Betz with the teaching of KOSTAS, which teaches a testing integrated circuit designs based on test cases selected using machine learning models in order to automate integrated chip testing (KOSTAS: 0003, the process of testing an integrated circuit using electronic design automation (EDA) tools may still be a very resource-intensive process.)
In regards to claim 5, Betz in view of KOSTAS teaches:
The dynamic selection method for the data region applied to the integrated circuit device according to claim 2, wherein the bias conditions corresponding to the bias condition variables are determined according to the plurality of selected first feature points and/or the plurality of selected second feature points; and the bias conditions comprise a data interval formed by the plurality of selected first feature points and/or second feature points. (0012 & 0004, FIG. 3A is a graph of a voltage cycling for testing of operating parameters; may determine a voltage level that is likely to work for worst-case scenario operating conditions (e.g., a minimum voltage that could allow that type of integrated circuit to operate;)
In regards to claim 6, Betz in view of KOSTAS teaches:
The dynamic selection method for the data region applied to the integrated circuit device according to claim 1, wherein the user instructions comprise manual instructions and machine instructions; and the dynamic selection method for the data region further comprises: storing the bias condition variables corresponding to the data item to be tested and/or the data item to be simulated; acquiring historical bias condition variables corresponding to the data item to be tested and/or the data item to be simulated in the case that the user instructions comprise at least one machine instruction; and acquiring at least one bias condition variable corresponding to the machine instructions through machine learning according to the historical bias condition variables. (0022, embodiments of the present disclosure relate generally to circuitry for enhancing performance of machine-readable programs implemented on an integrated circuit (IC). Indeed, such an IC may include a programmable logic device, such as a Field Programmable Gate Array (FPGA).)
In regards to claim 7, Betz in view of KOSTAS teaches:
The dynamic selection method for the data region applied to the integrated circuit device according to claim 1, wherein the dynamic test dataset changes dynamically according to changes in the test dataset; and/or the dynamic simulation dataset changes dynamically according to changes in the simulation dataset. (0045, FIG. 8 illustrates a detailed flow diagram view of a process 120 for dynamically varying temperature, voltage, and frequency. The FPGA is set to one of a number of calibration configurations to be tested (block 122).)
With regards to claim 8, Betz in view of KOSTAS teaches the dynamic selection system and corresponds to claim 1 as analyzed accordingly.
With regards to claim 9, Betz in view of KOSTAS teaches the dynamic selection device and corresponds to claim 1 to 7 as analyzed accordingly.
With regards to claim 10, Betz in view of KOSTAS teaches the computer-readable storage medium for dynamic selection system and corresponds to claim 1 to 7 as analyzed accordingly.
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
HYDE (US 2012/0212504 A1): A method of forming a compact model for an electrical device includes obtaining shape information for the device and obtaining nominal information for the device. The method also includes merging the shape information and the nominal information to form composite data, and fitting the compact model to the composite data.
Fournier (US 2002/0116694 A1): A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can
normally be reached Monday - Friday 8:00 - 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor,
Mark Featherstone can be reached on (571) 270-3750. The fax phone number for the organization
where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from
Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit
https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional
questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like
assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/ Primary Examiner, Art Unit 2111
3/19/2026