DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. These claims are directed towards a “One or more computer storage media” storing “instructions.”
The broadest reasonable interpretation of this phrase includes transitory media such as signals and carrier waves. Signals and carrier waves are forms of energy, which are non-statutory forms of patentable subject matter. Therefore, the Office recommends amending the claims so that they recite the phrase “non-transitory” with regard to “computer storage media”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 18 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. [US 2008/0243300 A1].
Regarding Claim 1, Liu teaches “A method comprising: identifying a computer program; and” as “the profile collector 10 interfaces with the processor's hardware profiling support 16 to monitor data cache miss events during program execution.” [¶0007]
“at each of a plurality of execution stages in which the computer program is to be executed: identifying an optimization profile that is to be used when compiling the computer program;” as “A software object layout optimizer then processes the data cache miss profile, automatically identifying the types of objects that cause most of the cache misses at run time.” [¶0005]
“generating, from the computer program and from the optimization profile, a cache key;” as “The just-in-time compiler generates load instruction maps for each compiled method.” [Abstract] (The mapping implies a key is involved. Also the mapping happens in the cache.)
“determining whether the cache key has an entry in a compilation cache that stores compilation outputs generated by a just-in-time compiler;” as “A profile collector is coupled to the just-in-time compiler to receive hardware profiling support. The profile collector takes samples of data cache misses.” [Abstract] (The profiling is used for determination of the location.)
“obtaining, based on whether the cache key is determined to have an entry in the compilation cache, a compilation output that either (i) was previously generated during a prior execution stage and stored in the compilation cache or (ii) is newly generated by the just-in-time compiler during the current execution stage; and” as “Once the hardware profiling support 16 is configured and started, it continuously monitors data cache miss events during program execution.” [¶0008] (During the current execution stage the determination (i.e., monitoring happens))
“providing the compilation output for execution of the computer program.” as “The just-in-time compiler 14 generates a load instruction map for each method it has compiled. The load instruction map is used to translate the instruction pointer address in the raw data cache miss samples into objects and object types (block 20). ” [¶0007] (The complier generates load instruction, which is executed by the computer.)
Claim 18 is anticipated by Liu under the same rationale of anticipation of claim 1.
Claim 19 is anticipated by Liu under the same rationale of anticipation of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. [US 2008/0243300 A1] in view of Kosche et al. [US 6,574,713 B1].
Claim 2 is rejected over Liu and Kosche.
Liu teaches “in response to determining that the cache key does not have an entry in the compilation cache, processing, by the just-in-time compiler and according to the optimization profile, the computer program to generate a compilation output.” as “Each sample includes an instruction pointer address, pointing to the load instruction that misses the data cache, and the address of the memory location targeted by the load instruction. The just-in-time compiler 14 generates a load instruction map for each method it has compiled.” [¶0007]
Liu does not explicitly teach wherein obtaining, based on whether the cache key is determined to have an entry in the compilation cache, a compilation output comprises: in response to determining that the cache key does have an entry in the compilation cache, obtaining, from the compilation cache, the compilation output corresponding to the cache key; and
However, Kosche teaches “wherein obtaining, based on whether the cache key is determined to have an entry in the compilation cache, a compilation output comprises: in response to determining that the cache key does have an entry in the compilation cache, obtaining, from the compilation cache, the compilation output corresponding to the cache key; and” as “For each set of offsets, the prefetch scheduler module 42 carries out the heuristic algorithm of the present invention to identify memory operations "guaranteed" to hit the cache as well as to define a "minimal" set of prefetches to insert.” [Col 5, lines 60-63]
Liu and Kosche are analogous arts because they teach cache memory management and access control of cache.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Liu and Kosche before him/her, to modify the teachings of Liu to include the teachings of Kosche with the motivation of prefetch instructions occupy space in the memory queue, it would be advantageous to avoid scheduling/inserting prefetches unnecessarily. [Kosche, Col 1, lines 61-63]
Claim 3 is rejected over Liu and Kosche.
Liu teaches “in response to processing the computer program to generate the compilation output, storing the generated compilation output as a new entry in the compilation cache, the new entry being associated with the cache key.” as “This can be done using the formula Address of the object's VTable Pointer equals the effective address of load target minus the offset, where effective address comes from the data cache miss sample and the offset is from the load instruction maps generated by the just-in-time compiler.” [¶0012]
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. [US 2008/0243300 A1] in view of Doshi et al. [US 2016/0321185 A1].
Claim 4 is rejected over Liu and Doshi.
Liu does not explicitly teach wherein the computer program defines a task comprising executing a trained machine learning model by performing operations comprising processing a model input to generate a model output representing a prediction about the model input.
However, Doshi teaches “wherein the computer program defines a task comprising executing a trained machine learning model by performing operations comprising processing a model input to generate a model output representing a prediction about the model input.” as “This stochastic bias technique allows software to guide hardware, or hardware to guide itself, based on statistics collected at runtime or by a machine learning algorithm that evaluates the positive or negative consequences of adjusting the biases based on performance of the system.” [¶0181]
Liu and Doshi are analogous arts because they teach cache memory management and access control of cache.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Liu and Doshi before him/her, to modify the teachings of Liu to include the teachings of Doshi with the motivation of a number of different execution units may be used to process and execute a variety of code and instructions. Some instructions may be quicker to complete while others may take a number of clock cycles to complete. The faster the throughput of instructions, the better the overall performance of the processor. [Doshi, ¶0043]
Claim 5 is rejected over Liu and Doshi.
Liu does not explicitly teach wherein the just-in-time compiler is a domain-specific compiler configured to compile computer programs that define machine learning models.
However, Doshi teaches “wherein the just-in-time compiler is a domain-specific compiler configured to compile computer programs that define machine learning models.” as “Applications of multiprocessor systems include dynamic domain partitioning all the way down to desktop computing. In order to take advantage of multiprocessor systems, code to be executed may be separated into multiple threads for execution by various processing entities. ” [¶0002]
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. [US 2008/0243300 A1] in view of Doshi et al. [US 2016/0321185 A1] and in further view of Chatterjee et al. [US 2007/0162703 A1].
Claim 6 is rejected over Liu, Doshi and Chatterjee.
The combination of Liu and Doshi does not explicitly teach wherein the just-in-time compiler is an accelerated linear algebra (XLA) compiler.
However, Chatterjee teaches “wherein the just-in-time compiler is an accelerated linear algebra (XLA) compiler.” as “It is another exemplary feature of the present invention to provide a technique in which a potential inefficiency inherent in compilers is addressed by using one or more lower-level memory management commands to override the compiler's normal sequence in matrix algebra processing.” [¶0025]
Liu, Doshi and Chatterjee are analogous arts because they teach cache memory management and access control of cache.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Liu, Doshi and Chatterjee before him/her, to modify the teachings of combination of Liu and Doshi to include the teachings of Chatterjee with the motivation of avoiding superfluous retrieval of data before writing data from cache into a target area in main memory. [Chatterjee, ¶0003]
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 recites this following allowable subject matter “wherein identifying an optimization profile that is to be used when compiling the computer program comprises: determining a profile key from the computer program; and identifying, using the profile key and from an optimization profile store that associates profile keys with optimization profiles, the optimization profile.”, which is not recited or fairly suggested by the prior arts of record.
Claims 8-17 are objected as well because they are all dependent on claim 7, which is objected by above justification.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/Primary Examiner, Art Unit 2132