DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Response to Amendment
Claims 1, 8, 12, 19, and 20 are amended.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 3 and 4 are objected to because of the following informalities: Claim 3 recites a first control point for the first transistor and a second control point for the second transistor. It is unclear if the first and second control points claimed in claim 1 and the first and second control points claimed in claim 3 are the same control points. The first and second control points of claim 3 appear to correspond to the first control point of claim 1 and the third and fourth control points of claim 4 appear to correspond to the second control point of claim 1. For the purposes of examination, the first and second control points of claim 3 will be interpreted to be contained within the first control point of claim 1 and the third and fourth control points of claim 4 will be interpreted to be contained within the second control point of claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. Korean Patent Document KR 10-2022-0045442 A (hereinafter “Yang”) and further in view of Wada et al. U.S. Patent Application 2018/0238968 (hereinafter “Wada”).
Regarding claim 1, Yang teaches a relay (refer to fig.2) of a battery management system, BMS (refer to figs.3 and 4), the relay comprising: a bus connection point (i.e. P+)(fig.2); a stack connection point (i.e. B+)(fig.2); a primary solid state relay, SSR (i.e. charging FET 110a and discharging FET 120a)(fig.2), electrically connected to the bus connection point and the stack connection point (implicit)(refer to fig.2), the primary SSR comprising: a first measurement point (i.e. first measurement point in the figure below)(fig.2) usable by the BMS for determining a first SSR state (refer to [0043] and [0054]); and a first control point (refer to first and second control point in the figure below)(fig.2) configured to selectively close the primary SSR when the primary SSR is in an open state (inherent)(refer to fig.2); a secondary SSR (i.e. charging FET 110b and discharging FET 120b)(fig.2) electrically connected to the bus connection point and the stack connection point (implicit)(refer to fig.2), the secondary SSR being connected in parallel to the primary SSR (implicit)(refer to fig.2) and comprising: a second measurement point (i.e. second measurement point in the figure below)(fig.2) usable by the BMS for determining a second SSR state (refer to [0043] and [0054]); and a second control point (refer to third and fourth control points in the figure below)(fig.2) configured to selectively close the secondary SSR when the secondary SSR is in an open state (inherent); however, Yang does not teach selectively closing the primary SSR based at least in part on a comparison of a battery parameter to a threshold; and selectively closing the secondary SSR based at least in part on the comparison of the battery parameter to the threshold. However, Wada teaches selectively closing the primary SSR based at least in part on a comparison of a battery parameter to a threshold (refer to [0024]-[0028]); and selectively closing the secondary SSR based at least in part on the comparison of the battery parameter to the threshold (refer to [0024]-[0028]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Yang to include the selective closing of Wada to provide the advantage of determining fault states of the switches, thereby preventing downtime of the circuit.
PNG
media_image1.png
473
793
media_image1.png
Greyscale
Regarding claim 2, Yang and Wada teach the relay of Claim 1, wherein the primary SSR comprises: a first transistor (i.e. Yang charging FET 110a)(fig.2) having a first source and a first drain (implicit)(refer to Yang fig.2); and a second transistor (i.e. Yang discharging FET 120a)(fig.2) having a second source and a second drain (implicit)(refer to Yang fig.2), the second transistor being connected in series to the first transistor (implicit)(refer to Yang fig.2), the first drain being electrically connected to the second drain (implicit)(refer to Yang fig.2), the first source being electrically connected to the stack connection point (implicit)(refer to Yang fig.2), the second source being electrically connected to the bus connection point (implicit)(refer to Yang fig.2).
Regarding claim 3, Yang and Wada teach the relay of Claim 2, wherein one or more of: the first measurement point is positioned between the first drain and the second drain (implicit)(refer to Yang fig.2); the first transistor comprises a first control point (i.e. Yang first control point in the figure above)(fig.2) arranged to receive a first control signal that triggers the first transistor to open or close (inherent); and the second transistor comprises a second control point (i.e. Yang second control point in the figure above)(fig.2) arranged to receive a second control signal that triggers the second transistor to open or close (inherent).
Regarding claim 4, Yang and Wada teach the relay of Claim 1, wherein the secondary SSR comprises: a third transistor (i.e. Yang charging FET 110b)(fig.2) having a third source and a third drain (implicit)(refer to Yang fig.2); and a fourth transistor (i.e. Yang discharging FET 120b)(fig.2) having a fourth source and a fourth drain (implicit)(refer to Yang fig.2), the fourth transistor being connected in series to the third transistor (implicit)(refer to Yang fig.2), the third drain being electrically connected to the fourth drain (implicit)(refer to Yang fig.2), the third source being electrically connected to the stack connection point (implicit)(refer to Yang fig.2), the fourth source being electrically connected to the bus connection point (implicit)(refer to Yang fig.2).
Regarding claim 5, Yang and Wada teach the relay of Claim 4, wherein one or more of: the second measurement point is positioned between the third drain and the fourth drain (implicit)(refer to Yang fig.2); the third transistor comprises a third control point (i.e. Yang third control point in the figure above)(fig.2) arranged to receive a third control signal that triggers the third transistor to open or close (inherent); and the fourth transistor comprises a fourth control point (i.e. Yang fourth control point in the figure above)(fig.2) arranged to receive a fourth control signal that triggers the fourth transistor to open or close (inherent).
Regarding claim 7, Yang and Wada teach the relay of Claim 1, wherein the primary SSR is a first metal-oxide-semiconductor field-effect transistor (i.e. Yang charging FET 110a and discharging FET 120a)(fig.2), MOSFET, SSR and the secondary SSR is a second MOSFET SSR (i.e. Yang charging FET 110b and discharging FET 120b)(fig.2).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang and Wada as applied to claim 1 above, and further in view of Xu et al. Chinese Patent Document CN 111030244 A (hereinafter “Xu”).
Regarding claim 6, Yang and Wada teach the relay of Claim 1; however, they do not teach wherein the secondary SSR is arranged to supply power while the primary SSR is one of diagnosed and open. However, Xu teaches wherein the secondary SSR is arranged to supply power while the primary SSR is one of diagnosed and open (refer to [0020]: “The battery group 1, then first control K1 is closed, K2 off, K3 off, delay or delays the preset time after 5 seconds, then control K1 open, K2 close, K3 close”). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the relay of Yang and Wada to include the secondary SSR supplying power while the primary SSR is open to provide the advantage of continuing supply of power during faults in order to minimize downtime.
Claim(s) 8-10, 13, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suyama et al. U.S. Patent Application 2022/0352729 (hereinafter “Suyama”) and further in view of Sung et al. U.S. Patent Application 2020/0106278 (hereinafter “Sung”).
Regarding claim 8, Suyama teaches a battery management system, BMS (refer to fig.1), comprising: a solid state relay, SSR (i.e. charge switch 2 and discharge switch 3)(fig.1)(refer also to [0038] and [0039]),; and processing circuitry (i.e. drive circuit 10, charge controller 20, monitoring unit 30, and judging unit 40)(fig.1) comprising a microcontroller unit, MCU (i.e. charge controller 20)(fig.1)(refer also to [0045]), the processing circuitry being electrically connected to the SSR (implicit)(refer to fig.1) and configured to: determine a failure mode associated with the MCU based on one or more parameters (refer to [0048]-[0052]); and cause the SSR, without MCU intervention, to perform one or more actions based on the failure mode (refer to [0048]-[0052]); and a cell monitor unit (i.e. drive circuit 10)(fig.1), CMU, electrically connectable to one or more battery cells (i.e. cells in the figure below)(fig.1); however, Suyama does not teach the CMU configured to determine a fault indication and transmit the fault indication to the MCU. However, Sung teaches the CMU (i.e. slave controller 100)(fig.1) configured to determine a fault indication (refer to [0067]) and transmit the fault indication to the MCU (i.e. master controller 200)(fig.1)(refer also to [0067]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Suyama to include the transmission of the fault indication of Sung to provide the advantage of simplifying the processing and connections required of the MCU, thereby allowing for a cheaper, less powerful processor.
PNG
media_image2.png
399
580
media_image2.png
Greyscale
Regarding claim 9, Suyama and Sung teach the BMS of Claim 8, wherein the processing circuitry further comprises: a cell monitor unit, CMU (i.e. Suyama drive circuit 10)(fig.1), electrically connectable to one or more battery cells (refer to Suyama battery 1)(fig.1); and a power management integrated circuit, PMIC (i.e. Suyama monitoring unit 30 and judging unit 40)(fig.1), in communication with the CMU (implicit)(refer to Suyama fig.1), one or both of the CMU and PMIC being configured to cause the SSR to perform the one or more actions based on the failure mode (refer to Suyama [0048]-[0052]).
Regarding claim 10, Suyama and Sung teach the BMS of Claim 9, wherein the CMU is configured to determine one or more parameters associated with the one or more battery cells (refer to Suyama [0044]).
Regarding claim 13, Suyama and Sung teach the BMS of Claim 9, wherein the PMIC is configured to determine the failure mode associated with the MCU based on a watchdog process usable for monitoring one or more MCU processes (refer to Suyama [0048]-[0052]).
Regarding claim 18, Suyama and Sung teach the BMS of Claim 8, wherein the one or more actions include one of disabling the SSR, enabling the SSR, opening the SSR, and closing the SSR (refer to Suyama [0048]-[0052]).
Regarding claim 19, Suyama teaches a battery (i.e. battery pack 100)(fig.1) comprising: one or more battery cells (refer to battery 1)(fig.1); a battery management system, BMS (i.e. charge switch 2, discharge switch 3, current detector 4, drive circuit 10, charge controller 20, monitoring unit 30, judging unit 40, and switcher 50)(fig.1), electrically connected to the one or more battery cells (implicit)(refer to fig.1), the BMS comprising: a solid state relay, SSR (i.e. charge switch 2 and discharge switch 3)(fig.1)(refer also to [0038] and [0039]), electrically connected to the one or more battery cells (implicit)(refer to fig.1); processing circuitry (i.e. drive circuit 10, charge controller 20, monitoring unit 30, and judging unit 40)(fig.1) comprising a microcontroller unit, MCU (i.e. charge controller 20)(fig.1)(refer also to [0045]), the processing circuitry being electrically connected to the SSR (implicit)(refer to fig.1) and configured to: determine a failure mode associated with the MCU based on one or more parameters (refer to [0048]-[0052]); and cause the SSR, without MCU intervention to perform one or more actions based on the failure mode (refer to [0048]-[0052]); and a cell monitor unit (i.e. drive circuit 10)(fig.1), electrically connectable to one or more battery cells (refer to cells in the figure above)(fig.1); however, Suyama does not teach the CMU configured to determine a fault indication and transmit the fault indication to the MCU. However, Sung teaches the CMU (i.e. slave controller 100)(fig.1) configured to determine a fault indication (refer to [0067]) and transmit the fault indication to the MCU (i.e. master controller 200)(fig.1)(refer also to [0067]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the battery of Suyama to include the transmission of the fault indication of Sung to provide the advantage of simplifying the processing and connections required of the MCU, thereby allowing for a cheaper, less powerful processor.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suyama and Sung as applied to claim 10 above, and further in view of Yamaguchi et al. U.S. Patent Application 2020/0227931 (hereinafter “Yamaguchi”).
Regarding claim 11, Suyama and Sung teach the BMS of Claim 10, wherein the MCU is in communication with the CMU (refer to Suyama fig.1); however, they do not teach the MCU is configured to determine parameter thresholds associated with the one or more parameters and transmit the parameter thresholds to the CMU. However, Yamaguchi teaches the MCU is configured to determine parameter thresholds associated with the one or more parameters (refer to [0082]) and transmit the parameter thresholds to the CMU (refer to [0082]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the BMS of Suyama and Sung to include the threshold transmission of Yamaguchi to provide the advantage of being able to adapt the thresholds to different loads.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suyama and Sung as applied to claim 8 above, and further in view of Hofer et al. U.S. Patent Application 2021/0028632 (hereinafter “Hofer”).
Regarding claim 14, Suyama and Sung teach the BMS of Claim 8; however, they do not teach wherein the processing circuitry further comprises a secondary current unit, SCU, configured to detect an overcurrent condition based on a predetermined hardware current threshold. However, Hofer teaches wherein the processing circuitry further comprises a secondary current unit, SCU (i.e. front end circuit 22)(fig.2), configured to detect an overcurrent condition based on a predetermined hardware current threshold (refer to [0074]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the BMS of Suyama and Sung to include the secondary current unit of Hofer to provide the advantage of protecting the battery and associated circuitry from damage due to overcurrent.
Regarding claim 15, Suyama, Sung, and Hofer teach the BMS of Claim 14, wherein the SCU is further configured to cause the SSR to perform one or more actions based on the detected overcurrent condition and the predetermined hardware current threshold (refer to Hofer [0074]).
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suyama and Sung as applied to claim 8 above, and further in view of Yang.
Regarding claim 16, Suyama and Sung teach the BMS of Claim 8, wherein the SSR comprises: a bus connection point (i.e. Suyama external terminal 5)(fig.1); a stack connection point (i.e. Suyama stack connection point in the figure above)(fig.1); and a primary solid state relay, SSR (i.e. Suyama charge switch 2 and discharge switch 3), electrically connected to the bus connection point and the stack connection point (implicit)(refer to Suyama fig.1); however, they do not teach the primary SSR comprising: a first measurement point usable by the BMS for determining a first SSR state. However, Yang teaches the primary SSR comprising: a first measurement point (i.e. first measurement point in the figure above)(fig.2) usable by the BMS for determining a first SSR state (refer to [0043] and [0054]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the BMS of Suyama and Sung to include the measurement of the SSR of Yang to provide the advantage of detecting failures within the SSR to protect the battery and associated circuitry from damage due to the SSR being stuck open or closed.
Regarding claim 17, Suyama, Sung, and Yang teach the BMS of Claim 16, wherein the SSR further comprises: a secondary SSR (i.e. Yang charging FET 110b and discharging FET 120b)(fig.2) electrically connected to the bus connection point and the stack connection point (implicit)(refer to Yang B+ and P+)(fig.2), the secondary SSR being connected in parallel to the primary SSR (implicit)(refer to Yang fig.2) and comprising: a second measurement point (i.e. Yang second measurement point in the figure above)(fig.2) usable by the BMS for determining a second SSR state (refer to Yang [0043] and [0054]).
Allowable Subject Matter
Claims 12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claim 12 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 12, especially wherein the CMU is configured to transmit the fault indication to the PMIC to cause the PMIC to enter an active mode of operation.
Claim 20 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 20, especially wherein one or more of: the processing circuitry further comprises: the cell monitor unit, CMU configured to determine one or more parameters associated with the one or more battery cells; and a power management integrated circuit, PMIC, in communication with the CMU, one or both of the CMU and PMIC being configured to cause the SSR to perform the one or more actions based on the failure mode; the MCU is in communication with the CMU and configured to determine parameter thresholds associated with the one or more parameters and transmit the parameter thresholds to the CMU; and the CMU is configured to determine a fault indication and transmit the fault indication to the MCU and the PMIC to cause the MCU and the PMIC to enter an active mode of operation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN J COMBER/Primary Examiner, Art Unit 2838
Prosecution Insights