DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7-14 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Sakakibara (WO 2020017353 A1, published on 2020-01-23. The reference is part of IDS).
[Examiner’s note – Although the rejection is based on publication # WO-2020017353 A1, published on 2020-01-23, Examiner is giving citation from equivalent national stage publication US 20210243399 A1, which is published in English]
Regarding Claim 1, Sakakibara discloses a photodetection element (1, fig. 1) comprising
a plurality of pixels (21, fig. 1, ¶0071-0072), wherein
each of the plurality of pixels comprises:
a physical signal acquisition unit that acquires a physical signal (152, fig. 6, ¶0082, ¶0119);
a comparison unit (61, figs. 2, 6) that compares a physical signal acquired by the physical signal acquisition unit with a reference signal (REF, fig. 6, ¶0086-0090);
a signal accumulation floating unit (163, fig. 6) that is electrically connected to one end of the comparison unit (fig. 6, ¶0123);
a signal detection unit (164, fig. 6) that is electrically connected to the signal accumulation floating unit (fig. 6) and detects a comparison result of the comparison unit (¶0124-0125);
a signal amplification unit (62, figs. 2, 6) that amplifies a detection result of the signal detection unit (¶0122, ¶0490);
a signal storage unit (72, figs. 2, 6) that stores a time code (…a signal storage unit 72 that stores the time code. – ¶0093);
a signal input/output unit (102, fig. 2) that inputs and outputs a time code (The time-code input/output unit 102 is supplied with a digital time code from the time-code generation unit 26, and the signal output from the signal storage unit 72 to the time-code input/output unit 102 – ¶0099); and
a signal control unit (71, figs. 2, 6) that performs control to store a time code output from the signal input/output unit (102, fig. 2) in the signal storage unit (72, figs. 2, 6) on a basis of the comparison result, and outputs, to the signal input/output unit, a time code of a time when the comparison result is inverted, the time code being stored in the signal storage unit (¶0093-0096), and
at least two or more of the pixels operate in parallel (parallel operation is evident from parallel architecture of pixels 21 as shown in fig. 1. Note that the write of a code and the drive of the comparator 61 are performed over all the pixels, simultaneously, resulting in a so-called global shutter operation – ¶0138).
Regarding Claim 7, Sakakibara discloses the photodetection element according to claim 1, wherein the signal amplification unit includes a positive feedback circuit (¶0089, 0091, ¶0122, 0124).
Regarding Claim 8, Sakakibara discloses the photodetection element according to claim 1, wherein the physical signal acquisition unit, the comparison unit, the signal accumulation floating unit, the signal detection unit, the signal amplification unit, the signal control unit, the signal storage unit, and the signal input/output unit are disposed across at least two semiconductor chips (figs. 3-4, ¶0103, 0107, 0111-0112, 0152).
Regarding claim 9, Sakakibara discloses the photodetection element according to claim 1, wherein the signal input/output unit is shared by a plurality of the physical signal acquisition units (Wiring replacement units are provided between a plurality of transfer paths allowing bitwise transfer of a predetermined bit length of time code for use in conversion of a pixel signal corresponding to a quantity of light received in a pixel into a digital signal - Abstract; As illustrated in FIG. 7, the time-code input/output unit 102 includes a transistor 190, a tri-state inverter 191, a tri-state buffer 192, FF circuits 201-1 to 201-N, buffer circuits 202-1 to 202-N, FF circuits 203-1 to 203-N, and buffer circuits 204-1 to 204-N connected together. Here, sets of the FF circuits and the buffer circuits are provided one-to-one to the latches 181 included in the signal storage unit 72, so that provided is a plurality of sets corresponding to the bit length that the signal storage unit 31 requires – ¶0128).
Regarding claim 10, Sakakibara discloses the photodetection element according to claim 1, wherein the signal input/output unit includes a flip-flop (Here, because the time-code input/output unit 102 includes flip-flops in multistage connection as illustrated in FIG. 7, the time code that is written into the latches 181 has a fixed offset shifted by 1 code at each location. – ¶0143.
FF circuits 201-1 to 201-N, buffer circuits 202-1 to 202-N, FF circuits 203-1 to 203-N … - ¶0128).
Regarding claim 11, Sakakibara discloses the photodetection element according to claim 1, wherein the signal input/output unit includes a tristate inverter (a tri-state inverter 191, a tri-state buffer 192 – ¶0128).
Regarding claim 12, Sakakibara discloses the photodetection element according to claim 1, wherein at least two of the signal storage units are provided (plural signal storage unit 72 is observed in fig. 6).
Regarding claim 13, Sakakibara discloses the photodetection element according to claim 12, wherein at least two of the signal input/output units are provided correspondingly to respective one of at least two of the signal storage units (limitation understood met in figs. 6-7, and ¶0128).
Regarding claim 14, Sakakibara discloses the photodetection element according to claim 12, further comprising a signal processing unit (111, fig. 2) that performs at least one of subtraction processing between signals stored in at least two of the signal storage units and image processing (Then, at timing T10, at the time of output at the signal level, the reset level temporarily stored in the SRAM is read out and subtraction is performed between the reset level and the signal level. – ¶0149).
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Kuroki (US 20070101177 A1).
Regarding Claim 15, Kuroki discloses a timing generator (fig. 3) comprising
a first circuit (104, fig. 3), a second circuit (106, fig. 3), and an arithmetic circuit (108, fig. 3), wherein
the first circuit (104, fig. 3) outputs, on a basis of one input signal (/CS, fig. 3), a first output signal obtained by delaying an inversion timing of the input signal, and an activation signal (signal that is input to block 106, fig. 3) that activates the second circuit (see fig. 4 how CLKEN2 is delayed and inverted with respect to /CS, ¶0073-0083),
the second circuit (106, fig. 3) is activated on a basis of the activation signal (signal that is input to block 106, fig. 3) and outputs a second output signal (see fig. 3), and
the arithmetic circuit (108, fig. 3) calculates the first output signal and the second output signal to output a third output signal (CLKEN2, fig. 3, ¶0073, ¶0081-0084).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakakibara in view of Yonemoto (US 20210314516 A1).
Regarding claim 6, Sakakibara discloses the photodetection element according to claim 1, except, wherein the comparison unit is shared by a plurality of the physical signal acquisition units.
However, Yonemoto discloses plurality of pixels, PX1-PX4 sharing a comparator 41 (fig. 2, ¶0260, 0322, 0335).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Sakakibara, using the teaching of Yonemoto of using a shared pixel, having plurality of photodiodes operating in binning mode as a pixel unit, which shares a single comparator, to obtain, wherein the comparison unit is shared by a plurality of the physical signal acquisition units, because, simple substitution of one known element for another to obtain predictable results is obvious. Furthermore, image sensors having shared pixels operate better in low lighting condition.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuroki.
Regarding claim 16, Kuroki discloses the timing generator according to claim 15, except, wherein the activation signal includes a first power supply voltage of the second circuit.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to make a first power supply voltage of the second circuit derived from the power supply voltage of the overall timing generator, and thus making the activation signal (which is defined as the signal that is input to block 106 [second circuit]) includes a first power supply voltage of the second circuit, because, the second circuit is a component of the overall timing generator. Such derivation can also be understood as obvious design choice, which does not raise any issues of criticality, and can be achieved by “Obvious to try” rationale under KSR – wherein, the solution is derived from choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success [see MPEP 21§2143.I].
Allowable Subject Matter
Claims 2-5, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior arts of record taken alone or in combination fails to reasonably disclose or suggest,
Regarding Claim 2, at least two pixel groups each of which detects a physical signal; and
a storage control unit that performs control, for the every pixel group, to store a time code in the signal storage unit and controls whether or not to update a time code stored in the signal storage unit.
Regarding Claim 3, wherein the comparison unit includes a transistor including a gate to which a physical signal acquired by the physical signal acquisition unit is input, a source to which the reference signal is input, and a drain electrically connected to the signal accumulation floating unit,
the comparison unit changes a voltage of the signal accumulation floating unit on a basis of a gate-source voltage of the transistor and a threshold of the transistor to enable the signal detection unit to perform detection, and
the signal detection unit is disposed in a pixel array unit.
Claims 4-5 are allowable for being dependent on allowable claim 3
Regarding Claim 17, wherein the second circuit includes a second power supply voltage of the first circuit in a period in which the second circuit is not activated.
Regarding Claim 18, wherein the first circuit and the second circuit include a first positive feedback circuit and a second positive feedback circuit that are connected in series.
Regarding Claim 19, an analog to digital (AD) converter comprising:
the timing generator according to claim 15;
a signal storage unit that stores a time code; and
a signal control unit that performs control to store a time code in the signal storage unit on a basis of the third output signal.
Claim 20, is allowable for being dependent on allowable claim 19.
Conclusion
The prior and/or pertinent art(s) made of record and not relied upon is considered pertinent to applicant's disclosure, are – Kawasaki (US 20210329188 A1), KITANO (US 20210235036 A1) – who disclose different ADC structured to be used in image sensors of interest.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHBAZ NAZRUL whose telephone number is (571)270-1467. The examiner can normally be reached M-Th: 9.30 am-3 pm, 6.30 pm-9 pm, F: 9.30 am-1.30 pm, 4 pm-8 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHBAZ NAZRUL/Primary Examiner, Art Unit 2638