Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-13 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Farmahini et al hereafter Farmahini (US pat. App. Pub. 20180165214) and in view of Kim (US pat. App. Pub. 20080034159).
3. As per claims 1, and 13, Farmahini discloses a secured semiconductor device, and a method comprising: a central processing unit (CPU); a micro-architectural store buffer; a micro-architectural load port; a micro-architectural line fill buffer, a cache memory; a primary memory; a cache bus allowing transfer of data at least from/to the central processing unit to/from the cache memory; a data system bus allowing transfer of data at least from/to the central processing unit to/from the primary memory; and a system address bus allowing transfer of addresses from/to the central processing unit to/from the primary memory (paragraphs: 19, and 32, wherein it emphasizes that CPU, buffer memory, Cache and port are connected to each other by data/address bus and they are able to transfer data and address to and from each other), wherein the central processing unit is provided with an instruction set, the instruction set comprising a regular first instruction operation code allowing to load data in the central processing unit from the primary memory through the data system bus, and a regular second instruction operation code allowing to store data from the central processing unit in the primary memory (paragraphs: 15, and 17, wherein it elaborates it elaborates that CPU and primary memory are connected to each other through the data bus and carrying instruction back and forth from the main memory), wherein the secured semiconductor device further comprises an additional secured bus for transfer of data from/to the central processing unit to/from the primary memory or an additional dedicated memory, the additional secured bus bypassing the micro-architectural load port and/or the micro-architectural line fill buffer, and/or the cache memory, and the instructions set of the central processing unit further implements two operations for a secured transfer, a first operation allowing to securely load data in the central processing unit from the primary memory or the additional dedicated memory, and a second operation allowing to securely store data from the central processing unit in the primary memory or the additional dedicated memory through the additional secured bus (12-13, and 26, wherein it deliberates that the CPU transfers the data/instruction to and from the memory by bypassing the Cache by using an additional bus). Although, Farmahini discusses about transferring data from CPU to main memory by bypassing Cache through a secured bus. In the same field of endeavor, Kim discloses load data in the central processing unit from the primary memory or the additional dedicated memory through the additional secured bus (paragraphs: 12, 14, and 36).
Accordingly, it would been obvious to one of ordinary skill in the network security art before the effective filing date of the claimed invention to have incorporated Kim’s teachings of load data in the central processing unit from the primary memory or the additional dedicated memory through the additional secured bus with the teachings of Farmahini, for the purpose of effectively protecting the data transfer from any unauthorized intruders.
5. As per claim 2, Farmahini and in view of Kim discloses the device, wherein the central processing unit comprises means for triggering the secure loading of data in the central processing unit from the primary memory through the additional secured bus and means for triggering the secure storage of data in the primary memory from the central processing unit through the additional secured bus, and in that said triggering depends on a confidentiality nature of the data (Farmahini, paragraphs: 36-37).
6. As per claim 3, Farmahini and in view of Kim discloses the device, wherein the means for triggering the secure loading or the secure storage of the data comprises a signal value that is encoded in the data (Farmahini, paragraphs: 42-43).
7. As per claim 4, Farmahini and in view of Kim discloses the device, wherein the means for triggering the secure loading or the secure storage of the data comprises a signal value that depends of an address (Farmahini, paragraphs: 30, and 44).
8. As per claim 5, Farmahini and in view of Kim discloses the device, wherein it comprises an additional dedicated memory, in that the additional secured bus connects the central processing unit to the additional dedicated memory, and in that data are securely loaded in the central processing unit through the additional secured bus upon use of the first operation allowing to securely load data in the central processing unit from the additional dedicated memory, and/or data are securely stored in the additional dedicated memory though the additional secured bus upon use of the second operation allowing to securely store data from the central processing unit (Farmahini, paragraphs: 12-13).
9. As per claim 6, Farmahini and in view of Kim discloses the device, wherein the additional secured bus is a partial virtual additional secured bus, the partial virtual additional secured bus having a bus path that physically correspond in part to the data system bus and the system address bus, but which has another part which bypasses some or all of the micro-architectural store buffer, the micro-architectural load port, the micro-architectural line fill buffer, and/or the cache memory (Farmahini, paragraphs: 15, and 18).
10. As per claim 7, Farmahini and in view of Kim discloses the device, wherein the additional secured bus is a virtual additional secured bus, and wherein, when the first or second operations are encountered, the micro-architectural store buffer and/or a micro-architectural load port and/or a micro-architectural line fill buffer and/or cache memory are flushed and disabled (Farmahini, paragraphs: 20-21).
11. As per claim 8, Farmahini and in view of Kim discloses the device, wherein the instruction set comprises an additional first opcode implementing the first operation and an additional second opcode implementing the second operation (Farmahini, paragraphs: 24-26).
12. As per claim 9, Farmahini and in view of Kim discloses the device, wherein the first operation allowing to securely load data in the central processing unit from the additional dedicated memory is initiated when encountering the regular first instruction operation code fetched from a predefined specific memory location and/or having an address of an operand within a specific memory area, and/or the second operation allowing to securely store data in the primary memory is initiated when encountering the regular second instruction operation code fetched from a predefined specific memory location and/or having an address of an operand within a specific memory area (Farmahini, paragraphs: 27-30).
13. As per claim 10, Farmahini and in view of Kim discloses the device, wherein it implements a reduced instruction set computer architecture (Farmahini, paragraphs: 33-34).
14. As per claim 11, Farmahini and in view of Kim discloses the device, wherein the reduced instruction set computer architecture is a reduced instruction set computer V architecture (Farmahini, paragraphs: 31-32).
15. As per claim 12, Farmahini and in view of Kim discloses the device, wherein it implements a complex instruction set computer architecture (Farmahini, paragraphs: 38, and 40).
Citation of References
16. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are cited but not been replied upon for this office action:
Ryu (US pat. app. Pub. 20060152981): discusses solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.
Burger et al (US pat. App. Pub. 20190236009): elaborates that performing wide memory operations for a wide data cache line. In some examples of the disclosed technology, a processor having two or more execution lanes includes a data cache coupled to memory, a wide memory load circuit that concurrently loads two or more words from a cache line of the data cache, and a writeback circuit situated to send a respective word of the concurrently-loaded words to a selected execution lane of the processor, either into an operand buffer or bypassing the operand buffer. In some examples, a sharding circuit is provided that allows bitwise, byte-wise, and/or word-wise manipulation of memory operation data. In some examples, wide cache loads allows for concurrent execution of plural execution lanes of the processor.
Conclusion
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD W REZA whose telephone number is (571)272-6590. The examiner can normally be reached on Monday-Friday 8:30-5:30 ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Cathy Thiaw can be reached on 571-270-1138. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/MOHAMMAD W REZA/Primary Examiner, Art Unit 2407
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