Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1–20 have been submitted for examination.
Claims 1–6 and 16–17 have been examined and rejected.
Claims 7–15 and 18–20 are objected to.
Allowable Subject Matter
Claims 7–15 and 18–20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1–6 and 16–17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (US 2011/0193970) in view of Lau et al. (US 2020/0014969).
Regarding claim 1, Zhu discloses:
A data processing device comprising:
a clock data recovery unit (“video clock recovery circuit 100”) that extracts a clock and data on a basis of baseband video data in a first format corresponding to a predetermined transmission path, (Zhu, ¶ [0019], “The system 200 has a video clock recovery circuit 100 which has a reference input 101 derived from the link clock Flink and a Ratio modulator M/N 107 that is used to modulate the output frequency 110.”) the baseband video data being input from the predetermined transmission path; (Zhu, Fig. 2, transmission path 220, ¶ [0019], “A FIFO 210 is provided to store the video data received. […]. The data input is 220 and the data output from the FIFO is 222.”) and
a processing unit that processes the extracted data (Zhu, ¶ [0019], “Once the initial data value 212 is reached, the monitor circuit 211 continuously monitors the level of data in the FIFO 210 to detect any high level 214, 216, 218 or low level 213, 215, 217 crossing of the data in the FIFO. The Fvid value is kept constant as long as the data level remains within the levels 213 to 214 or until it crosses any of the other levels.”) on a basis of the extracted clock,. (Zhu, ¶ [0043], “This exemplary and non-limiting flow described allows the feedback generated and hence the Fvid 110 to remain stable till the data in the FIFO crosses a high data level 214, 216 or 218 or a low data level 213, 215 or 217, at which time the monitor circuit 211 generates a signal corresponding to the level and sends it 232 to the Mf and Nf value adjuster circuit 240. This enables the adjustment of the value of the integers Mf and Nf 241 by the Mf and Nf adjuster circuit 240. The change in feedback to the ratio modulator 107 in the clock recovery circuit 100 allows the regenerated Fvid 110 to change.”)
Zhu does not explicitly teach “wherein the processing unit outputs dummy data capable of clock extraction at a subsequent stage in a case where occurrence of jitter-fluctuation is detected”.
In a similar field of endeavor Lau teaches:
wherein the processing unit outputs dummy data (Lau, ¶ [0113], “Various embodiments perform such a comparison immediately prior to output to ensure that the data is output at the appropriate time. Other embodiments use such a comparison to insert the media data into a playback buffer at a position where the media is likely to be played back at the presentation time. Such insertion may involve the insertion of “dummy” data prior to insertion of the media data to adjust the timing of the playback.”) capable of clock extraction at a subsequent stage in a case where occurrence of jitter-fluctuation (“variable delay” includes jitter) is detected (Lau, ¶ [0111], “In the case where the sender timestamp has been translated, the translated timestamp is used in calculating the offset. This offset value, “O,” is equivalent to the true offset between the sender and receiver clocks plus any delay encountered by the media data message between the creation of the two timestamps, S(x) and R(x), including both fixed and variable delay.”)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the system for clock data recovery as taught by Zhu with the system for generating dummy data as taught by Lau, the motivation is “to adjust the timing of the playback” as taught by Lau (¶ [0113]).
Regarding claim 2, the combination of Zhu and Lau teaches:
The data processing device according to claim 1, wherein the predetermined transmission path is an optical communication network. (Lau, ¶ [0149], “Components of the electronic devices can also include […] circuits of optical networks or other communication networks”)
Regarding claim 3, the combination of Zhu and Lau teaches:
The data processing device according to claim 1, wherein the processing unit outputs baseband video data in a second format (“DisplayPort”), and the baseband video data in the second format is baseband video data corresponding to a predetermined wired interface (“DisplayPort”). (Zhu, ¶ [0016], “During transmission and reception of a video data stream in the display port system the data and control information are transmitted as packets over a high speed link using spread spectrum.”)
Regarding claim 4, the combination of Zhu and Lau teaches:
The data processing device according to claim 3, wherein the predetermined wired interface is an HDMI or a DisplayPort (“DisplayPort”). (Zhu, ¶ [0016], “During transmission and reception of a video data stream in the display port system the data and control information are transmitted as packets over a high speed link using spread spectrum.”)
Regarding claim 5, the combination of Zhu and Lau teaches:
The data processing device according to claim 1, wherein the dummy data is copy (Lau, ¶ [0077], “In some embodiments, a duplicate packet can be inserted into the staging buffer”, ¶ [0096], “a duplicate of a previous packet can be rendered in place of the missing packet”) video data (Lau, ¶ [0113], “Various embodiments perform such a comparison immediately prior to output to ensure that the data is output at the appropriate time. Other embodiments use such a comparison to insert the media data into a playback buffer at a position where the media is likely to be played back at the presentation time. Such insertion may involve the insertion of “dummy” data prior to insertion of the media data to adjust the timing of the playback.”) in units of frames (“within 1 to 3 frames”) or lines. (Lau, ¶ [0071], “the video can be briefly buffered based on an average or minimum expected transmission and processing time. The buffering time can be estimated based on network tests (e.g., tests discussed with respect to blocks 405 and 407 of FIG. 4), and the buffering time can be selected such that the audio will play at or just after (e.g., within 1 to 3 frames) of the video.”)
Regarding claim 6, the combination of Zhu and Lau teaches:
The data processing device according to claim 1, wherein the clock data recovery unit (Zhu, ¶ [0018], “The initially transmitted integer values Mvid and Nvid are used in the clock recovery circuit 100, to extract an initial value of the stream clock Fvid from the link clock Flink.”) continues to output a clock (Zhu, ¶ [0016], “The link clock Flink is different from the frequency of the data video stream clock Fvid”) in a state immediately after occurrence of jitter-fluctuation in a case where the occurrence of the jitter-fluctuation is detected. (Zhu, ¶ [0043], “Increasing the value of Fvid 110 if the stored data value 221 crosses a low data level 213, 215, or 217, increases the unpacking speed to increase the rate of data 220 loading into the FIFO 210. Alternately, decreasing the value of Fvid 110 if the data level 221 crossed a high data level 214, 216 or 218 reduces the unpacking speed to reduce the data 220 loading into the FIFO 210.”)
Regarding claim 16, Zhu discloses:
A data processing method comprising:
a clock data recovery procedure of extracting a clock and data (Zhu, ¶ [0019], “The system 200 has a video clock recovery circuit 100 which has a reference input 101 derived from the link clock Flink and a Ratio modulator M/N 107 that is used to modulate the output frequency 110.”) on a basis of baseband video data input from a predetermined transmission path and having a format corresponding to the predetermined transmission path; (Zhu, Fig. 2, 220, ¶ [0019], “A FIFO 210 is provided to store the video data received. […]. The data input is 220 and the data output from the FIFO is 222.”) and
a processing procedure of processing the extracted data (Zhu, ¶ [0019], “Once the initial data value 212 is reached, the monitor circuit 211 continuously monitors the level of data in the FIFO 210 to detect any high level 214, 216, 218 or low level 213, 215, 217 crossing of the data in the FIFO. The Fvid value is kept constant as long as the data level remains within the levels 213 to 214 or until it crosses any of the other levels.”) on a basis of the extracted clock,. (Zhu, ¶ [0043], “This exemplary and non-limiting flow described allows the feedback generated and hence the Fvid 110 to remain stable till the data in the FIFO crosses a high data level 214, 216 or 218 or a low data level 213, 215 or 217, at which time the monitor circuit 211 generates a signal corresponding to the level and sends it 232 to the Mf and Nf value adjuster circuit 240. This enables the adjustment of the value of the integers Mf and Nf 241 by the Mf and Nf adjuster circuit 240. The change in feedback to the ratio modulator 107 in the clock recovery circuit 100 allows the regenerated Fvid 110 to change.”)
Zhu does not explicitly teach “wherein in the processing procedure, in a case where occurrence of jitter-fluctuation is detected, dummy data capable of clock extraction at a subsequent stage is output.”.
In a similar field of endeavor Lau teaches:
wherein in the processing procedure, in a case where occurrence of jitter-fluctuation (“variable delay” includes jitter) is detected, dummy data. (Lau, ¶ [0113], “Various embodiments perform such a comparison immediately prior to output to ensure that the data is output at the appropriate time. Other embodiments use such a comparison to insert the media data into a playback buffer at a position where the media is likely to be played back at the presentation time. Such insertion may involve the insertion of “dummy” data prior to insertion of the media data to adjust the timing of the playback.”) capable of clock extraction at a subsequent stage is output (Lau, ¶ [0111], “In the case where the sender timestamp has been translated, the translated timestamp is used in calculating the offset. This offset value, “O,” is equivalent to the true offset between the sender and receiver clocks plus any delay encountered by the media data message between the creation of the two timestamps, S(x) and R(x), including both fixed and variable delay.”)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the system for clock data recovery as taught by Zhu with the system for generating dummy data as taught by Lau, the motivation is “to adjust the timing of the playback” as taught by Lau (¶ [0113]).
Regarding claim 17, Zhu discloses:
A data processing device comprising:
a clock data recovery unit that extracts a clock and data, (Zhu, ¶ [0019], “The system 200 has a video clock recovery circuit 100 which has a reference input 101 derived from the link clock Flink and a Ratio modulator M/N 107 that is used to modulate the output frequency 110.”) (Zhu, Fig. 2, 220, ¶ [0019], “A FIFO 210 is provided to store the video data received. […]. The data input is 220 and the data output from the FIFO is 222.”) and
on a basis of input data, (Zhu, ¶ [0019], “Once the initial data value 212 is reached, the monitor circuit 211 continuously monitors the level of data in the FIFO 210 to detect any high level 214, 216, 218 or low level 213, 215, 217 crossing of the data in the FIFO. The Fvid value is kept constant as long as the data level remains within the levels 213 to 214 or until it crosses any of the other levels.”) (Zhu, ¶ [0043], “This exemplary and non-limiting flow described allows the feedback generated and hence the Fvid 110 to remain stable till the data in the FIFO crosses a high data level 214, 216 or 218 or a low data level 213, 215 or 217, at which time the monitor circuit 211 generates a signal corresponding to the level and sends it 232 to the Mf and Nf value adjuster circuit 240. This enables the adjustment of the value of the integers Mf and Nf 241 by the Mf and Nf adjuster circuit 240. The change in feedback to the ratio modulator 107 in the clock recovery circuit 100 allows the regenerated Fvid 110 to change.”)
Zhu does not explicitly teach “wherein in a case where an input of data not capable of clock extraction is detected, the clock data recovery unit continues to output a clock in a state immediately after an input of the data.”.
In a similar field of endeavor Lau teaches:
wherein in a case where an input of data not capable of clock extraction is detected (“variable delay” includes jitter), (Lau, ¶ [0111], “In the case where the sender timestamp has been translated, the translated timestamp is used in calculating the offset. This offset value, “O,” is equivalent to the true offset between the sender and receiver clocks plus any delay encountered by the media data message between the creation of the two timestamps, S(x) and R(x), including both fixed and variable delay.”) the clock data recovery unit continues to output a clock in a state immediately after an input of the data. (Lau, ¶ [0113], “Various embodiments perform such a comparison immediately prior to output to ensure that the data is output at the appropriate time. Other embodiments use such a comparison to insert the media data into a playback buffer at a position where the media is likely to be played back at the presentation time. Such insertion may involve the insertion of “dummy” data prior to insertion of the media data to adjust the timing of the playback.”)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the system for clock data recovery as taught by Zhu with the system for generating dummy data as taught by Lau, the motivation is “to adjust the timing of the playback” as taught by Lau (¶ [0113]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL B PIERORAZIO whose telephone number is (571)270-3679. The examiner can normally be reached on Monday - Thursday, 8am - 5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nasser Goodarzi can be reached on 5712704195. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL B. PIERORAZIO/Primary Examiner, Art Unit 2426