DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-3) in the reply filed on 8/10/2026 is acknowledged.
Claims 4-5 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected subject matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko et al. (US Patent 10849225).
Regarding claim 1 – Ko teaches a mounting substrate (fig. 1 [title] Ko states, “printed circuit board”) comprising: an insulating layer (12 [column 4 line 6] Ko states, “the insulating layer 12”); and a plurality of conductive bumps (24 & 26 [column 4 lines 5-6] Ko states, “a pad 24, and a post 26”) arranged on or above the insulating layer (both bumps 24 & 26 are considered “on” the insulating layer 12), wherein a variation in height position between a plurality of first end faces (top faces) of the plurality of conductive bumps (24 & 26) on a side opposite to the insulating layer (12) is smaller than a variation in height position between a plurality of second end faces (bottom face) of the plurality of conductive bumps (24 & 26) on a side where the insulating layer (12) is located (annotated figure 1 below shows the top face of conductive bumps 24 & 26 being coplanar having a smaller variation in height than the bottom face of the conductive bumps).
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Regarding claim 2 – Ko teaches the mounting substrate according to claim 1, further comprising: a wiring layer (fig. 1, 22 [column 4 line 5] Ko states, “pattern 22”) located on or above the insulating layer (12, the wiring layer 22 is considered to be “on” the insulating layer 12), wherein a height position of a third end face (top surface of wiring layer 22 shown in annotated figure 1 above) of the wiring layer (22) on the side opposite to the insulating layer (12) is closer to the insulating layer (12) than a height position of each of the plurality of first end faces is (figure 1 shows the wiring layer 22 third end face being coplanar closer with the insulating layer 12 than the first end faces that are shown to protrude above the insulating layer 12).
Regarding claim 3 – Ko teaches the mounting substrate according to claim 1, wherein the insulating layer (fig. 1, 12) includes a via hole (see via holes below conductive bumps 24 [column 4 lines 50-52] Ko states, “a via passing through the first insulating layer 12 may be connected to the lower surface of the pad 24”), and the mounting substrate further comprises: a via electrode (see conductive material with the via holes) located in the via hole, overlapping with a specific conductive bump (24) of the plurality of conductive bumps (24 & 26) in a plan view, and electrically connected to the specific conductive bump (claimed structure shown in figure 1).
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huemoeller et al. (US Patent 7589398).
Regarding claim 1 – Huemoeller teaches a mounting substrate (fig. 5D) comprising: an insulating layer (501D [column 19 line 62] Huemoeller states, “dielectric layer 501D”); and a plurality of conductive bumps (508D and combined 565D & 511D [columns 19 & 20 lines 65-66 & 1-2] Huemoeller states, “bias trace 508D…bias trace 565D…bias trace 511D”) arranged on or above the insulating layer (501D), wherein a variation in height position between a plurality of first end faces (top faces) of the plurality of conductive bumps (508D and combined 565D & 511D) on a side opposite to the insulating layer (501D) is smaller than a variation in height position between a plurality of second end faces (bottom face) of the plurality of conductive bumps (508D and combined 565D & 511D) on a side where the insulating layer (501D) is located (figure 5D shows the top face of conductive bumps 508D & 565D/511D being coplanar having a smaller variation in height than the bottom face of the conductive bumps which shows one conductive bump on the upper surface of the insulating layer and the other being embedded within the insulating layer).
Regarding claim 2 – Huemoeller teaches the mounting substrate according to claim 1, further comprising: a wiring layer (fig. 5D, 510D [column 19 line 67] Huemoeller states, “signal trace 510D”) located on or above the insulating layer (501D), wherein a height position of a third end face (top surface of wiring layer 510D) of the wiring layer (510D) on the side opposite to the insulating layer (501D) is closer to the insulating layer (501D) than a height position of each of the plurality of first end faces is (figure 1 shows the wiring layer 510D third end face being closer with the insulating layer 501D than the first end faces of the conductive bumps 508D & 565D/511D).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Weng et al. (US Patent 12414232) discloses a substrate structure having minor height variation at an upper surface of contacts.
Choi et al. (US PG. Pub. 2017/0176804) discloses bumps with different heights.
Kodani (US PG. Pub. 2010/0314254) discloses a wiring substrate with different sized pad thicknesses.
Liu et al. (US PG. Pub. 2020/0303334) discloses a semiconductor device and package.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
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