DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1, 2, 4-12, 14-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4-12, 14-20, respectively, of copending Application No. 18/861,284 (‘284) in view of Dietrich – US 2018/0343016 and Kim et al. – US 2022/0147482 (Kim)
Present application
‘284
Claim 1:
A transmitter comprising: a serialization circuit configured to convert parallel data into serial data with one or more serialization stages; a logic circuit electrically coupled to the serialization circuit and an output circuit, the logic circuit configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of the output circuit, wherein the logic circuit is connected to a low voltage supply domain; and the output circuit configured to implement output stages to generate a signal based on the received input using p-channel metal oxide semiconductor (PMOS) field effect transistors.
Claim 1:
A transmitter comprising: a serialization circuit configured to convert parallel data into serial data with one or more serialization stages; a logic circuit electrically coupled to the serialization circuit and an output circuit, the logic circuit configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of the output circuit;
and the output circuit configured to implement output stages to generate a signal based on the received input using n-channel metal oxide semiconductor (NMOS) field effect transistors, wherein the ground of the logic circuit is configured to be a desired voltage value.
‘284 differs from the claimed invention in that it does not recite the underlined claimed subject matter.
Dietrich, in similar filed of endeavor, discloses “logic circuit” (Fig. 1, element 16) coupled to the “serialization circuit” (Fig. 1, element 14) and the output circuit (Fig. 1, elements 18, 22) that discloses the underlined claimed subject matter in para. 0027.
Kim discloses output using both NMOS and PMOS in para. 0036.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the filing to have incorporated the teaching from Dietrich and Kim into claim 1 of ‘284 for at least improving the speed of data rate (Dietrich, para. 0004, 0017).
Claim 2:
The transmitter of claim 1, wherein the dedicated output stage is a PMOS based trans-conductance (gm) stage
Claim 2:
The transmitter of claim 1, wherein the dedicated output stage is an NMOS based trans-conductance (gm) stage. Note: based on combination in claim 1 above, output stage is an PMOS.
Claim 4:
The transmitter of claim 1, wherein: the serialization circuit includes a series of multiplexers in the one or more serialization stages, the last serialization stage is an n: 1 multiplexer, and the logic circuit is configured to connect n bits input from the last serialization stage to n gm stages through n logic function.
Claim 4:
The transmitter of claim 1, wherein: the serialization circuit includes a series of multiplexers in the one or more serialization stages, the last serialization stage is an n: 1 multiplexer, and the logic circuit is configured to connect n bits input from the last serialization stage to n gm stages through n logic function.
Claim 5:
The transmitter of claim 4, wherein the input of the last serialization stage is connected to the respective output stage with a relevant clock phase.
Claim 5:
The transmitter of claim 4, wherein the input of the last serialization stage is connected to the respective output stage with a relevant clock phase.
Claim 6:
The transmitter of claim 5, wherein the serialization circuit and the output circuit are connected by the logic circuit in a way that reduces data load of the last serialization stage and increases operation speed of the transmitter.
Claim 6:
The transmitter of claim 5, wherein the serialization circuit and the output circuit are connected by the logic circuit in a way that reduces data load of the last serialization stage and increases operation speed of the transmitter.
Claim 7:
The transmitter of claim 1, wherein each output stage is fed with digital data and output to a common resistor load to generate an analog symbol.
Claim 7:
The transmitter of claim 1, wherein each output stage is fed with digital data and output to a common resistor load to generate an analog symbol.
Claim 8:
The transmitter of claim 1, further comprising: a data acquisition circuit configured to generate the parallel data in a plurality of data branches, wherein the serialization circuit and the logic circuit are configured to convert the parallel data received from the plurality of data branches into a single sequence of data.
Claim 8:
The transmitter of claim 1, further comprising: a data acquisition circuit configured to generate the parallel data in a plurality of data branches, wherein the serialization circuit and the logic circuit are configured to convert the parallel data received from the plurality of data branches into a single sequence of data.
Claim 9:
The transmitter of claim 1, wherein the transmitter is one of a digital-to-analog converter (DAC) based transmitter, a non-return-to-zero (NRZ) transmitter, or other types of transmitters.
Claim 9:
The transmitter of claim 1, wherein the transmitter is one of a digital-to-analog converter (DAC) based transmitter, a non-return-to-zero (NRZ) transmitter, or other types of transmitters.
Claim 10:
The transmitter of claim 1, wherein the logic circuit is connected to a controlled supply and adjusted to enable a current source to operate in saturation.
Claim 10:
The transmitter of claim 1, wherein the logic circuit is connected to an external reference voltage and adjusted to enable a current source to operate in saturation. Note: the external reference voltage can includes “controlled supply” since the reference can be “controlled”.
Claim 11:
A method for configuring and implementing a transmitter, comprising: receiving, by a serialization circuit, data in parallel from a plurality of data branches, the serialization circuit including one or more serialization stages; connecting each input of a last stage of the one or more serialization stages, via a respective logic function of a logic circuit, to a respective dedicated output stage of an output circuit; connecting the logic circuit to a low voltage supply domain; and implementing, by the output circuit, output stages to generate a signal based on the received input using p-channel metal oxide semiconductor (PMOS) field effect transistors.
Claim 11:
A method for configuring and implementing a transmitter, comprising: receiving, by a serialization circuit, data in parallel from a plurality of data branches, the serialization circuit including one or more serialization stages; connecting each input of a last stage of the one or more serialization stages, via a respective logic function of a logic circuit, to a respective dedicated output stage of an output circuit; and implementing, by the output circuit, output stages to generate a signal based on the received input using n-channel metal oxide semiconductor (NMOS) field effect transistors, wherein the ground of the logic circuit is configured to be a desired voltage value.
‘284 differs from the claimed invention in that it does not recite the underlined claimed subject matter.
Dietrich, in similar filed of endeavor, discloses “logic circuit” (Fig. 1, element 16) coupled to the “serialization circuit” (Fig. 1, element 14) and the output circuit (Fig. 1, elements 18, 22) that discloses the underlined claimed subject matter in para. 0027.
Kim discloses output using PMOS in para. 0036.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the filing to have incorporated the teaching from Dietrich and Kim into claim 1 of ‘284 for at least improving the speed of data rate (Dietrich, para. 0004, 0017).
Claim 12:
The method of claim 11, wherein the dedicated output stage is a PMOS based trans-conductance (gm) stage.
Claim 12:
The method of claim 11, wherein the dedicated output stage is a NMOS based trans-conductance (gm) stage. Note: based on combination in claim 11 above, output stage is an PMOS.
Claim 14:
The method of claim 11, further comprising: configuring a series of multiplexers in the one or more serialization stages of the serialization circuit, wherein the last serialization stage is an n: 1 multiplexer, and connecting, by the logic circuit, n bits input from the last serialization stage to n gm stages through n logic functions.
Claim 14:
The method of claim 11, further comprising: configuring a series of multiplexers in the one or more serialization stages of the serialization circuit, wherein the last serialization stage is an n: 1 multiplexer, and connecting, by the logic circuit, n bits input from the last serialization stage to n gm stages through n logic functions.
Claim 15:
The method of claim 14, wherein the input of the last serialization stage is connected to the respective output stage with a relevant clock phase.
Claim 15:
The method of claim 14, wherein the input of the last serialization stage is connected to the respective output stage with a relevant clock phase.
Claim 16:
The method of claim 15, wherein the serialization circuit and the output circuit are connected by the logic circuit in a way that reduces data load of the last serialization stage and increases operation speed of the transmitter.
Claim 16:
The method of claim 15, wherein the serialization circuit and the output circuit are connected by the logic circuit in a way that reduces data load of the last serialization stage and increases operation speed of the transmitter.
Claim 17:
The method of claim 11, wherein each output stage is fed with digital data and output to a common resistor load to generate an analog symbol.
Claim 17:
The method of claim 11, wherein each output stage is fed with digital data and output to a common resistor load to generate an analog symbol.
Claim 18:
The method of claim 11, further comprising: generating the data in the plurality of data branches, and converting the data received in parallel from the plurality of data branches into a single sequence of data.
Claim 18:
The method of claim 11, further comprising: generating the data in the plurality of data branches, and converting the data received in parallel from the plurality of data branches into a single sequence of data.
Claim 19:
The method of claim 11, wherein the transmitter is one of a digital-to-analog converter (DAC) based transmitter, a non-return-to-zero (NRZ) transmitter, or other types of transmitters.
Claim 19:
The method of claim 12, wherein the transmitter is one of a digital-to-analog converter (DAC) based transmitter, a non-return-to-zero (NRZ) transmitter, or other types of transmitters.
Claim 20:
The method of claim 11, further comprising: connecting the logic circuit to a controlled supply; and adjusting the logic circuit to enable a current source to operate in saturation.
Claim 20:
The method of claim 12, further comprising: connecting the logic circuit to an external reference voltage; and 18adjusting the logic circuit to enable a current source to operate in saturation. Note: the external reference voltage can include “controlled supply” since the reference can be “controlled”.
This is a provisional nonstatutory double patenting rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Eitan et al. – US 2025/0286758
Hsieh et al. – US 2023/0253975
Ucar – US 11,469,760
Saeki – US 10,784,906
Peng et al. – US 10,728,060
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/DAC V HA/ Primary Examiner, Art Unit 2633