DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 102a1 as being anticipated by Maderic et al. (US 20230043376).
Regarding claim 1, Maderic teaches a system comprising:
a photo detector 606;
one or more processing components comprising one or more digitization circuits operatively coupled to the photo detector, one or more level shifters, and a microcontroller operatively coupled to the one or more digitization circuits through the one or more level shifters, and a first part of an input/output (I/O) connector, the microcontroller comprising one or more of: an analog to digital converter (ADC), a processor, an EVENT system (EVSYS), a capture control unit (CCU), a general-purpose input/output (GPIO), and a universal asynchronous receiver-transmitter (UART) interface (para 52); and
one or more I/O components operatively coupled to the one or more processing components, the one or more I/O components comprising one or more of a communications interface, protection circuitry, and a second part of the I/O connector (par 52).
Regarding claim 2, Maderic teach the one or more processing components further comprise: a reference voltage source operatively coupled to the digitization circuit through a buffer amplifier (para 52).
Regarding claim 3 Maderic teach the reference voltage is approximately 4.096 V (para 47, 52-53).
Regarding claim 4, Maderic teaches the reference voltage source is operatively coupled to the ADC through the buffer amplifier (para 49).
Regarding claim 5, Maderic teaches the one or more processing components are disposed on a first board and the one or more I/O components are disposed on a second board (para 47).
Regarding claim 6, Maderic teaches the one or more digitization circuits comprise one or more of: an integrating amplifier; a 2:1 multiplexor; an ADC; and one or more external integrating capacitors (para 70).
Regarding claim 7, Maderic teaches the one or more level shifters convert one or more signals received from the one or more processing components at about 1.8 V to one or more signals sent to the digitization circuit at about 5 V and converts one or more signals received from the digitization circuit at about 5 V to one or more signals sent to the one or more processing components at about 1.8 V (para 70).
Regarding claim 8, Maderic teaches the one or more signals received from the one or more processing components comprise a convert (CONV) signal from the EVSYS (para 47).
Regarding claim 9, Maderic teaches the one or more signals received from the one or more processing components comprise digital controls for the one or more digitization circuits (para 47).
Regarding claim 10, Maderic teaches the one or more processing components further comprise: one or more ambient temperature sensors operatively coupled to the ADC (para 52
Regarding claim 11, Maderic teaches the one or more processing components further comprise: a system clock and a memory operatively coupled to the processor, the memory storing computer-readable instructions that, when executed by the processor, generate a CONV signal based off a timing signal from the system clock (para 52-53).
Regarding claim 12, Maderic teaches the CONV signal extends a natural period of the integration of the one or more digitization circuits from a few milliseconds to as long as desired (para 52-53).
Regarding claim 13, Maderic teaches the system clock and the one or more digitization circuits operate at a clock rate of about 15 MHz (para 52-53).
Regarding claim 14, Maderic teaches the one or more processing components further comprise: a power supply operatively coupled to the first part of the I/O connector, the power supply configured to step down an input voltage of about 24 VDC to an operating voltage of the one or more processing components (para 52-53).
Regarding claim 15, Maderic teaches the first part of the I/O connector and the second part of the I/O connector are configured to be attached and detached (para 47).
Regarding claim 16, Maderic teaches the communications interface is configured for communications through one or more interfaces and/or protocols comprising Ethernet, EtherCAT, CAN, ProfiBus, ProfiNet, and USB (para 46).
Regarding claim 17, Maderic teaches the protection circuitry comprises one or more fuses configured in series and a transient-voltage-suppression (TVS) diode (para 52-53).
Regarding claim 18, Maderic teaches one or more of the one or more processing components and the one or more I/O components are disposed on a printed circuit board (PCB) having a thickness of approximately 0.8mm (para 47
Regarding claim 19, Maderic teaches the one or more digitization circuits convert an analog signal from the photo detector proportional to an intensity of infrared (IR) radiation to a 20-bit digital number (para 3).
Regarding claim 20, Maderic teaches the EVSYS is a peripheral that allows other peripherals on the one or more processing components to signal directly to each other independently of the processor (para 52-53).
Claim(s) 1 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lu et al. (US 20210116564).
Regarding claim 1, Brown teaches a system comprising:
a photo detector;
one or more processing components comprising one or more digitization circuits operatively coupled to the photo detector, one or more level shifters, and a microcontroller operatively coupled to the one or more digitization circuits through the one or more level shifters, and a first part of an input/output (I/O) connector, the microcontroller comprising one or more of: an analog to digital converter (ADC), a processor, an EVENT system (EVSYS), a capture control unit (CCU), a general-purpose input/output (GPIO), and a universal asynchronous receiver-transmitter (UART) interface (para 33); and
one or more I/O components operatively coupled to the one or more processing components, the one or more I/O components comprising one or more of a communications interface, protection circuitry, and a second part of the I/O connector (par 21).
Claim(s) 1 5 and 10 are rejected under 35 U.S.C. 102a1 as being anticipated by Brown et al.(WO 2016081841).
Regarding claim 1, Brown teaches a radiometric temperature measurement system comprising:
a photo detector 120;
one or more processing components comprising one or more digitization circuits operatively coupled to the photo detector, one or more level shifters 156, and a microcontroller 128 operatively coupled to the one or more digitization circuits through the one or more level shifters, and a first part of an input/output (I/O) connector 154, the microcontroller comprising one or more of: an analog to digital converter (ADC), a processor, an EVENT system (EVSYS), a capture control unit (CCU), a general-purpose input/output (GPIO), and a universal asynchronous receiver-transmitter (UART) interface; and
one or more I/O components operatively coupled to the one or more processing components, the one or more I/O components comprising one or more of a communications interface 154, protection circuitry, and a second part of the I/O connector (see EP 23812482, PCT written opinion).
Regarding claim 5, Brown teaches the one or more processing components are disposed on a first board and the one or more I/O components are disposed on a second board (element 124).
Regarding claim 10, Brown teaches the one or more processing components further comprise: one or more ambient temperature sensors operatively coupled to the ADC (142).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown.
Regarding claims 2-3, Brown fails to teach the one or more processing components further comprise: a reference voltage source operatively coupled to the digitization circuit through a buffer amplifier and the reference voltage is approximately 4.096 V.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adapt the claimed reference voltage since it would provide proper voltage to operate the device.
Regarding claim 4, Brown teaches the reference voltage source is operatively coupled to the ADC through the buffer amplifier (ADC 126).
Regarding claim 6, Brown teaches the one or more digitization circuits comprise one or more of: an integrating amplifier; a 2:1 multiplexor; an ADC; and one or more external integrating capacitors.
Regarding claim 7, Brown fails to teach the one or more level shifters convert one or more signals received from the one or more processing components at about 1.8 V to one or more signals sent to the digitization circuit at about 5 V and converts one or more signals received from the digitization circuit at about 5 V to one or more signals sent to the one or more processing components at about 1.8 V.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adapt the claimed level shifters since it would provide proper voltage to operate the device.
Regarding claim 8, Brown teaches the one or more signals received from the one or more processing components comprise a convert (CONV) signal from the EVSYS (not limitative).
Regarding claim 9, Brown teaches the one or more signals received from the one or more (not limitative).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOON K SONG whose telephone number is (571)272-2494. The examiner can normally be reached M to Th 10am to 7pm.
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/HOON K SONG/Primary Examiner, Art Unit 2884
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