DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 15, 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oda et al. (US 2021/0083672).
Claim 1, Oda discloses a look-up-table (Fig. 2 and see P[0020]…LUT…) comprising:
a plurality of programmable memory cells (Memory M1-M16); and
a plurality of multiplexers connected in multiple stages (stages 1241 – 1244) to form a tree-like structure (see Fig. 2), wherein a first stage of said multiple stages (stage 1241) is connected to said plurality of programmable memory cells (Memory M1-M16) and has a greatest number of said multiplexers of all of said multiple stages;
wherein a last stage of said multiple stages (stage 1244) has a least number of said multiplexers and is configured to forward a look-up table output (Out) that is a selected memory state of one of said plurality of memory cells;
wherein each of said plurality of multiplexers comprises at least two transistors (see P[0023]…The transfer gate 125.sub.1i (i=1, . . . , 16) includes a p-channel MOS transistor and an n-channel MOS transistor…); and
at least one inverter (any inverter from a plurality of inverters 124e11 – 124e32) connected to an output of at least one of said plurality of multiplexers; and
input select pins (In1 – In4) of said plurality of multiplexers configured to connect to input sources to provide input to said look-up-table.
Claim 2, Oda discloses the look-up table of claim 1, comprising a plurality of said inverters (124e11 – 124e32), wherein outputs of every stage of said multiple stages are connected to inputs of said inverters; and outputs of said inverters are connected to inputs of a subsequent stage of multiplexers, except for one of said inverters connected to said multiplexer in said last stage (only one inverter 124e41, Fig. 2).
Claim 3, Oda discloses the look-up table of claim 1, wherein inputs provided to said input select pins are all independent of one another (In1, In2, In3, and In4 are independent).
Claim 4, Oda discloses the look-up table of claim 1 or claim 2, further comprising buffers (inverters 124e21 – 124e24) between at least two of said stages of said multiple stages of multiplexers.
Claim 5, Oda discloses the look-up table of claim 4, wherein said buffers comprise additional ones of said inverters (any one of inverter from the inverters 124e21 – 124e24 can be additional inverter).
Claim 15, Oda discloses the look-up table of claim 1, wherein the look-up table output is configured to write the state of the programmable memory cell cells (Memory M1-M16 are configuration memory (see P[0020]… a configuration memory (hereinafter also referred to as “memory”) 122..) which are configurable or write into it).
Claim 17, Oda discloses the look-up table of claim 1, wherein said plurality of multiplexers comprise two-input to one-output multiplexers (each multiplexer included two-input to one-output, see Fig. 2) and said tree-like structure is a binary tree arrangement, said plurality of multiplexers being arranged and configured to forward one said selected memory state (one of state from Memories M1 – M13, Fig. 2); wherein each said multiplexer comprises one p-channel metal-oxide-semiconductor field-effect transistor and one n-channel metal-oxide-semiconductor field-effect transistor (see P[0023]…The transfer gate 125.sub.1i (i=1, . . . , 16) includes a p-channel MOS transistor and an n-channel MOS transistor…); and wherein said look-up table comprises look-up table input pins (pins In1 – In4, Fig. 4), each of said look-up-table input pins being connected to said select input signals of said multiplexers in each said stage (different stages connected to different input pins, see Fig. 2).
Claim 18, Oda discloses the look-up table of claim 1, wherein each of said multiplexers comprises one or more memory cells with state outputs that are used to multiplex two or more look-up-table inputs; each output of said memory cells with state outputs is connected to a select input signal of one of said of multiplexers in one of the levels of said tree-like structure (see Fig. 2).
Claim 19, Oda discloses the look-up table of claim 18, wherein said multiplexers are two-input to one-output multiplexers (each multiplexer included two-input to one-output, see Fig. 2), each said multiplexer comprising one p-channel metal-oxide- semiconductor field-effect transistor and one n-channel metal-oxide-semiconductor field-effect transistor (see P[0023]…The transfer gate 125.sub.1i (i=1, . . . , 16) includes a p-channel MOS transistor and an n-channel MOS transistor…); and wherein one of said memory cell state outputs is connected to one of a gate of said p-channel transistor and a gate of said n-channel transistor to forward one of two inputs (each transfer gate included a p-channel MOS transistor and an n-channel MOS transistor and each gate is connected to input In1 – In4 to output one of two inputs).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oda et al. (US 2021/0083672) in view of Yasuda et al. (US 2013/0257477).
Oda discloses the invention substantially as claimed, but does not disclose wherein at least one of said plurality of programmable memory cells comprises: a static random access memory bit cell, a resistance change element, a single magneto-resistive random-access memory bit cell, a phase change material, a metal-oxide-metal system, or a single dynamic random-access memory bit cell.
In the same field of endeavor, Yasuda discloses memory cells for LUT can be either volatile memories or nonvolatile memories (see P[0047]… memories of the memory groups 21a and 21b may be either volatile memories or nonvolatile memories…) and further discloses the nonvolatile memories can be a floating type flash memory, a charge-trap type metal-oxide-nitride-oxide-semiconductor (MONOS) memory, a phase-change memory, MRAM, an ionic memory, and a resistance change type memory such as a resistance random access memory (ReRAM) (see P[0048] and Figs. 13A-14).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to provide wherein at least one of said plurality of programmable memory cells comprises: a static random access memory bit cell, a resistance change element, a single magneto-resistive random-access memory bit cell, a phase change material, a metal-oxide-metal system, or a single dynamic random-access memory bit cell, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice.
3. Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oda et al. (US 2021/0083672) in view of Chirania et al. (US 7,116,131).
Claim 13, Oda discloses the invention substantially as claimed, but does not disclose wherein said look-up table output is pre-charged to a predetermined state before forwarding the selected memory cell state.
In the same field of endeavor, Chirania discloses a look-up table output is pre-charged to a predetermined state before forwarding the selected memory cell state (see Figs. 17, 22 and col. 17, lines 48-63,… when signal PHI is low, both LUT output signals LUT_OUT, LUT_OUTB are high (the pre-charge state)…).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to provide the look-up table output with a precharged circuit, as taught by Chirania, in order to increase the look-up table performance and speed.
Claim 14, Oda and Chirania discloses the look-up table of claim 13, further comprising a transistor (transistor 2201, Fig. 22 of Chirania) to set said look-up table output to said predetermined state (high state).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oda et al. (US 2021/0083672) in view of Ho (US 2016/0203860).
Oda discloses the invention substantially as claimed, but does not disclose further comprising a control circuitry to enable write to the programmable memory cells.
In the same field of endeavor, Ho a LUT (Figs. 9-10, and 12) further comprising a control circuitry (100, 200, transistor 121, and 122) to enable write to the programmable memory cells.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to provide the LUT with a control circuitry of Ho to enable write to the programmable memory cells, as taught by Ho, in order to prevent an excessive current from flowing between the terminals of a resistive change element when the state of the resistive change element is changed from the HRS to the LRS, thus, prevent the resistive change element from being programmed in error.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gopinath et al. (US 2023/0260561), Oda et al. (US 2013/0235688), and Chirania et al. (US 7,385,416) disclose a look-up-table comprising: a plurality of programmable memory cells; and a plurality of multiplexers connected in multiple stages to form a tree-like structure, wherein a first stage of said multiple stages is connected to said plurality of programmable memory cells and has a greatest number of said multiplexers of all of said multiple stages; wherein a last stage of said multiple stages has a least number of said multiplexers and is configured to forward a look-up table output that is a selected memory state of one of said plurality of memory cells.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANH Q TRAN/Primary Examiner, Art Unit 2845 6/4/26
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