DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This communication is a first office action, non-final rejection on the merits. Claims 1-11, as originally filed, are currently pending and have been considered below.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim 8 is rejected under 35 U.S.C. 102 (a) (1) as being anticipated by
Nishino (WO-2020/045125A1).
As Per Claim 8, Nishino teaches, a light receiving device ( via a light receiving element and distance measuring device) comprising: a first light receiving element; a quench element connected between a first node that is an anode or a cathode of the first light receiving element and a node of a first power supply voltage; ( via the light-receiving element comprising a pixel array 112 in which pixels 121 are two-dimensionally arranged in a matrix in the row direction and the column direction,); a transistor connected between a node of the first power supply voltage and a node of a second power supply voltage; ( via : one pixel 121 among the plurality of pixels 121 has an SPAD 211 (corresponding to the "first light-receiving element"), a transistor 212 (corresponding to the "quenching element") acting as a quenching resistance that is provided between a cathode (corresponding to the "first node") of the SPAD 211 and a power source voltage VE (corresponding to the "first power source voltage"), and transistors 161, 162 (corresponding to the "transistor") connected between the power source voltage VE (corresponding to the "first power source voltage") and ground (corresponding to the "second power source voltage"); a second light receiving element; and a diode element connected between a second node that is an anode or a cathode of the second light receiving element and a node of the second power supply voltage and connected to the second light receiving element in a polarity relationship in a reverse direction, wherein the first light receiving element and the second light receiving element receive a predetermined voltage at a node opposite to the first node and the second node. (via another pixel 121 among of the plurality of pixels 121 has an SPAD 211 (corresponding to the "second light-receiving element"), and a body diode 172 (corresponding to the "diode element") that is connected between a cathode (corresponding to the "second node") of the SPAD 211 and ground (corresponding to the "second power source voltage") and connects to the SPAD 211 in a reverse polarity relationship as illustrated in fig. 10, and an anode (corresponding to the "node on the opposite side from the first node and the second node") of the SPAD 211 is connected to a power source VSPAD (corresponding to the "prescribed voltage") ([0001], 0029], [0040], [0084], [0088], [0095], Figs. 2, 10-12).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
6. Claims 1-7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Nishino (WO-2020/045125A1 in view of Nakazawa (USP 2017/0163836A1).
As Per Claim 1, Nishino teaches, a light receiving device ( via a light receiving element and distance measuring device) comprising: an effective pixel including a light receiving element that detects presence or absence of photons and a readout circuit of a pixel which processes a signal output from the light receiving element; ( via the light-receiving element comprising a pixel array 112 in which pixels 121 are two-dimensionally arranged in a matrix in the row direction and the column direction,); a first terminal configured to apply a predetermined voltage to a light receiving element of the effective pixel and a light receiving element of the dummy pixel; a second terminal configured to provide a first power supply voltage to the readout circuit; ( via : one pixel 121 among the plurality of pixels 121 has an SPAD 211 (corresponding to the "first light-receiving element"), a transistor 212 (corresponding to the "quenching element") acting as a quenching resistance that is provided between a cathode (corresponding to the "first node") of the SPAD 211 and a power source voltage VE (corresponding to the "first power source voltage"), and transistors 161, 162 (corresponding to the "transistor") connected between the power source voltage VE (corresponding to the "first power source voltage") and ground (corresponding to the "second power source voltage"); a protection circuit including a diode element connected between a light receiving element and the second terminal in a polarity relationship in a reverse direction with respect to a light receiving element a, and protecting a light receiving element of the effective pixel and a circuit element of the readout circuit from overvoltage (via another pixel 121 among of the plurality of pixels 121 has an SPAD 211 (corresponding to the "second light-receiving element"), and a body diode 172 (corresponding to the "diode element") that is connected between a cathode (corresponding to the "second node") of the SPAD 211 and ground (corresponding to the "second power source voltage") and connects to the SPAD 211 in a reverse polarity relationship as illustrated in fig. 10, and an anode (corresponding to the "node on the opposite side from the first node and the second node") of the SPAD 211 is connected to a power source VSPAD (corresponding to the "prescribed voltage") ([0001], 0029], [0040], [0084], [0088], [0095], Figs. 2, 10-12).
However, Nishino does not explicitly teach, a dummy pixel including a light receiving element that does not contribute to detection of presence or absence of photons; a protection circuit including a diode element connected between a light receiving element of the dummy pixel and the second terminal in a polarity relationship in a reverse direction with respect to a light receiving element of the dummy pixel, and protecting a light receiving element of the effective pixel and a circuit element of the readout circuit from overvoltage.
In an analogous art, Nakazawa teaches photoelectric transducer, image reading device, image forming apparatus, and image reading method, wherein, a dummy pixel (via light-shielding pixel) including a light receiving element that does not contribute to detection of presence or absence of photons; a protection circuit including a diode element connected between a light receiving element of the dummy pixel and the second terminal in a polarity relationship in a reverse direction with respect to a light receiving element of the dummy pixel, and protecting a light receiving element of the effective pixel and a circuit element of the readout circuit from overvoltage ( via “a photoelectric transducer 10 , having Each of a PIX(R) 20, a PIX(G) 22, and a PIX(B) 24 includes approximately 7,000 PDs (photodiodes) (light-receiving elements) and is configured for a corresponding one of colors R, G, and B (Red, Green, and Blue). The PDs, which are included in pixels, are arranged in parallel rows, each row corresponding to one of colors of to-be-received light. Each of the PDs creates a charge that depends on the amount of received light. Each of the PIX(R) 20, the PIX(G) 22, and the PIX(B) 24 includes light-shielding pixel areas 40 on both ends. The light-shielding pixel area 40 includes a plurality of light-shielded pixels (OPBs (OPtical Black)). The light-shielded pixel includes, as do the other pixels, a PD but differs from the other pixels in being light-shielded.”, [0040], [0079], [0086], Fig.5).
It would have been obvious to one of ordinary skill in the art, having the teachings of Nishino and Nakazawa before him before the effective filing date of the claimed invention to modify the systems of Nishino , to include the teachings ( light shielded pixel (dummy pixel) of Nakazawa and configure with the system of Nishino , in order to calculate an offset amount of an effective pixel at a desired position by arranging the light-shielding pixel area 40 on each of a leading end and a trailing end in the main-scanning direction of each of the PIX(R) 20, the PIX(G) 22, and the PIX(B) 24 and performing linear interpolation using pixel data (offset amounts) of the OPBs in each of the light-shielding pixel areas 40 and a pixel address. Motivation to combine the two teachings is, to apply offset correction even when the magnitude of the influence of the SSC varies from one pixel position to another in the main-scanning direction in the photoelectric transducer.
As per Claim 2, Nishino as modified by Nakazawa teaches the limitation of Claim 1. However, Nishino in view of Nakazawa teaches, a first substrate including a light receiving element of the effective pixel and a light receiving element of the dummy pixel; and a second substrate including the readout circuit and the protection circuit. (Nakazawa: [0040], [0079], [0086], Fig.5). (See rationale supporting obviousness and motivation to combine, of claim 1 above).
As per Claim 3, Nishino as modified by Nakazawa teaches the limitation of Claim 1. However, Nishino in view of Nakazawa teaches, wherein a light receiving element of the effective pixel and a light receiving element of the dummy pixel are avalanche diodes. (Nishino : via “distance image sensors employ a pixel array in which pixels using SPAD (Single Photon Avalanche Diode) are arranged in a matrix” [0002]-[0008]).
As per Claim 4, Nishino as modified by Nakazawa teaches the limitation of Claim 3. However, Nishino in view of Nakazawa teaches, wherein a light receiving element of the effective pixel and a light receiving element of the dummy pixel are single photon avalanche diodes. ( Nishino : via “distance image sensors employ a pixel array in which pixels using SPAD (Single Photon Avalanche Diode) are arranged in a matrix” [0002]-[0008]).
As per Claim 5, Nishino as modified by Nakazawa teaches the limitation of Claim 4. However, Nishino in view of Nakazawa teaches, wherein a single photon avalanche diode of a dummy pixel adjacent to a dummy pixel to which the diode element belongs is used as the diode element. ( Nakazawa: via “a photoelectric transducer 10 , having Each of a PIX(R) 20, a PIX(G) 22, and a PIX(B) 24 includes approximately 7,000 PDs (photodiodes) (light-receiving elements) and is configured for a corresponding one of colors R, G, and B (Red, Green, and Blue). The PDs, which are included in pixels, are arranged in parallel rows, each row corresponding to one of colors of to-be-received light. Each of the PDs creates a charge that depends on an amount of received light. Each of the PIX(R) 20, the PIX(G) 22, and the PIX(B) 24 includes light-shielding pixel areas 40 on both ends. The light-shielding pixel area 40 includes a plurality of light-shielded pixels (OPBs (OPtical Black)). The light-shielded pixel includes, as do the other pixels, a PD but differs from the other pixels in being light-shielded.”, [0040], Fig.5). (See rationale supporting obviousness and motivation to combine, of claim 1 above).
As per Claim 6, Nishino as modified by Nakazawa teaches the limitation of Claim 4. However, Nishino in view of Nakazawa teaches, a third terminal configured to apply a second power supply voltage to a readout circuit of the effective pixel; and at least one of a surge current path including a diode element connected to a light receiving element of the dummy pixel in a polarity relationship in a forward direction between the first terminal and the second terminal or a surge current path including a diode element connected to a light receiving element of the dummy pixel in a polarity relationship in a forward direction between the first terminal and the third terminal. (Nakazawa: [0040], [0079], [0086], Fig.5). (See rationale supporting obviousness and motivation to combine, of claim 1 above).
As per Claim 7, Nishino as modified by Nakazawa teaches the limitation of Claim 1. However, Nishino in view of Nakazawa does not explicitly teach, wherein a readout circuit of the effective pixel is configured using a thin film transistor.
However, a readout circuit of the effective pixel being configured using a thin film transistor, would be an obvious matter of design choice, In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975).
Claim 11 is being rejected using the same rationale as claim 1.
7. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Nishino (WO-2020/045125A1) in view of Nakazawa (USP 2017/0163836A1).
As per Claim 9, Nishino teaches the limitation of Claim 8. However, Nishino does not explicitly teach, wherein the first light receiving element is arranged in an effective pixel region, and the second light receiving element is arranged in a dummy pixel region.
In an analogous art, Nakazawa teaches photoelectric transducer, image reading device, image forming apparatus, and image reading method, wherein the first light receiving element is arranged in an effective pixel region, and the second light receiving element is arranged in a dummy pixel region ( via “a photoelectric transducer 10 , having Each of a PIX(R) 20, a PIX(G) 22, and a PIX(B) 24 includes approximately 7,000 PDs (photodiodes) (light-receiving elements) and is configured for a corresponding one of colors R, G, and B (Red, Green, and Blue). The PDs, which are included in pixels, are arranged in parallel rows, each row corresponding to one of colors of to-be-received light. Each of the PDs creates a charge that depends on the amount of received light. Each of the PIX(R) 20, the PIX(G) 22, and the PIX(B) 24 includes light-shielding pixel areas 40 on both ends. The light-shielding pixel area 40 includes a plurality of light-shielded pixels (OPBs (OPtical Black)). The light-shielded pixel includes, as do the other pixels, a PD but differs from the other pixels in being light-shielded.”, [0040], [0079], [0086], Fig.5).
It would have been obvious to one of ordinary skill in the art, having the teachings of Nishino and Nakazawa before him before the effective filing date of the claimed invention to modify the systems of Nishino , to include the teachings ( light shielded pixel (dummy pixel) of Nakazawa and configure with the system of Nishino , in order to calculate an offset amount of an effective pixel at a desired position by arranging the light-shielding pixel area 40 on each of a leading end and a trailing end in the main-scanning direction of each of the PIX(R) 20, the PIX(G) 22, and the PIX(B) 24 and performing linear interpolation using pixel data (offset amounts) of the OPBs in each of the light-shielding pixel areas 40 and a pixel address. Motivation to combine the two teachings is, to apply offset correction even when the magnitude of the influence of the SSC varies from one pixel position to another in the main-scanning direction in the photoelectric transducer.
8. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nishino (WO-2020/045125A1) in view of Okamoto (USP 2017/0365224).
As per Claim 10, Nishino teaches the limitation of Claim 8. However, Nishino does not explicitly teach, a first substrate including the first light receiving element and the second light receiving element; and a second substrate including the quench element, the transistor, and the diode element.
In an analogous art, Okamoto teaches, display device , display module and electronic device, wherein, a first substrate including the first light receiving element and the second light receiving element; and a second substrate including the quench element, the transistor, and the diode element ([0196], also see [0080], [0195], Figs. 1A-2A).
It would have been obvious to one of ordinary skill in the art, having the teachings of Nishino and Okamoto before him before the effective filing date of the claimed invention to modify the systems of Nishino to include the teachings
(light-receiving element 190, diode connected transistor etc.) of Okamoto and configure with the system of Nishino in order to augment electronic amplification with respect to the amount of incident light. Motivation to combine the two teachings is, to reduce power consumption.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUHAMMAD SHAFI whose telephone number is (571)270-5741. The examiner can normally be reached M-F 8:30 am -5:00 pm.
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/MUHAMMAD SHAFI/ Primary Examiner, Art Unit 3666C
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