DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-10 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/02/2024 and 09/08/2025 have been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 8, 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIRIBUCHI (US Pub. 2024/0186924) in view of TAKEDA (US 2015/0333550).
Regarding claims 1, 8, 9 and 10,
KIRIBUCHI teaches the inventive concept recited in independent claims 1, 8, 9 and 10, characterized by an identification information receiving device ([0043] teaches, “the controller 41 of the servo driver 4 receives the encoder identification information.”, thus corresponding to said receiving device) that receives identification information defined by a plurality of bits from an identification information transmitting device ([0043] teaches, “encoder identification information … is transmitted from the processing unit 221 of the encoder 22 to the servo driver 4”, thus corresponding to said transmitting device) connected to the identification information receiving device via a power line ([0043] teaches, “connecting the servo driver 4 and the motor 2 by the power line 11.” and further teaches “identification information is transmitted through … the power line 11.”), the identification information being superimposed on a current or a voltage of the power line by the identification information transmitting device ([0034] teaches, “AC power obtained by superimposing the predetermined signal on the coil of the winding unit 25 …” thereby teaches that the predetermined signal is superimposed on AC power, the resulting current corresponding to the signal is extracted).
Kiribuchi fails to expressly teach that the identification information receiving device comprises the recited structure.
TAKEDA teaches an integration circuit that integrates an input signal that indicates a voltage value corresponding to the current or the voltage of the power line (teaches in [0115] that the calculator (e11) for average current value executes a process of calculating an average value of the current inputted from the current detector (22) in a predetermined cycle to output the result to the adders (e12, e14) thus teaching integration of an input signal, time-based averaging and the production of an averaged output signal);
a subtraction circuit that subtracts an output signal of the integration circuit from the input signal([0118] teaches "The adder e14 subtracts the predetermined value from the average current value inputted from the calculator e11 for average current value to output the result to the adder e15. The adder e15 subtracts the detected value Idc by the current detector 22 from the output value of the adder e14 to output the result to the comparator e6 and the PI controller e7. That is, the adder e15 outputs the value obtained by adding a predetermined value to the fluctuation amount in current values to the comparator e6 and the PI controller e7." e11 produces an integrate/averaged signal and e15 subtracts the detected current value from the averaged value); and
a binary converter that determines an output signal of the subtraction circuit as one when the output signal of the subtraction circuit is greater than or equal to a threshold value, and determines zero when the output signal of the subtraction circuit is less than the threshold value ([0059] teaches "The adder e5 subtracts the current value Idc from the threshold Lim_d (<0) to output to the comparator e6 ..." and [0062]-[0064] teach "When the charging current...is equal to or below threshold Lim_c (output of comparator e2:'0'" and "When...above threshold Lim_c (output of comparator e2:'1' ", thus teaching comparison with a threshold; binary outputs (0/1) and threshold based determination.)
Before the effective filing date of the invention it would have been obvious to combine the teachings of Kiribuchi and Takeda and to use Takeda’s known signal processing technique for the purpose of more accurately extracting the superimposed identification signal transmitted over the power line as taught by Kiribuchi.
Regarding claim 2,
Takeda teaches the identification information receiving device according to claim 1, wherein the binary converter includes a comparison circuit that compares the output signal of the subtraction circuit with the threshold value and outputs a high-level signal or a low-level signal depending on a result of the comparing (see [0054]-[0058]; [0056] teaches, “When a current difference (ldc-Lim_c) is above 0, the comparator e2 outputs ‘1’…when 0 or below, outputs ‘0’).
Regarding claim 4,
Takeda teaches that the integration circuit includes a low-pass filter, and a time constant of the low-pass filter includes a cutoff frequency is at most 1/10 of a clock frequency corresponding to a communication speed of the identification information ([0115] teaches “calculator e11 for average current value executes process of calculating average value in a predetermined cycle”; [0117] teaches use of (idc – i_AVE); and [0120] teaches comparing fluctuation relative to average, thus constituting an averaging/integration function. It is important to note that an averaging process over a predetermined cycle is functionally equivalent to a low-pass filtering/integration process; [0115] teaches predetermined cycle averaging. One or ordinary skill in the art would configure the low-pass filter time constant so that the cutoff is less than or equal to 1/10 of the clock frequency to achieve stable detection and control).
Allowable Subject Matter
Claims 3 and 5, 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3,
The prior art fails to further teach the identification information receiving device according to claim 1, wherein the subtraction circuit includes an operational amplifier including a single power supply, and the input signal is input to a non-inverting input terminal of the operational amplifier, and the output signal of the integration circuit is input to an inverting input terminal of the operational amplifier.
Regarding claim 5,
The prior art fails to further teach that the integration circuit includes a RC circuit and a voltage follower.
Regarding claim 6,
The prior art fails to further teach that an authentication period that includes reception of the identification information ends, a power supply to an active element that is included in each of the integration circuit, the subtraction circuit, and the comparison circuit is blocked.
Regarding claim 7,
The prior art fails to further teach a removable and portable electricity storage pack that serves as the identification information receiving device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIONNE PENDLETON whose telephone number is (571)272-7497. The examiner can normally be reached M-F 9a-5pm.
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/DIONNE PENDLETON/Primary Examiner, Art Unit 2689