Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are made.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kitagawa (US 2009/0039833) in view of Sakai (JP-2000286905-A).
Regarding clams 1, 9, 10 and 11 Kitagawa teaches an identification information receiving device that receives identification information defined by a plurality of bits (see Figs. 3-5), the identification information being superimposed on a current or a voltage of a power line by an identification information transmitting device that is connected to the identification information receiving device via the power line (see para 0038 0060 and 0065; Fig. 5), the identification information receiving device comprising:
However, Kitagawa does not disclose an edge detector that detects an edge of an input signal that indicates a voltage value corresponding to the current or the voltage of the power line and a T flip-flop circuit that inverts an output of the T flip-flop circuit each time the edge of the input signal is detected
Yet, Sakai in the same field teaches an edge detector that detects an edge of an input signal that indicates a voltage value corresponding to the current or the voltage of the power line (see rising and falling edges of this pulse modulated wave para 0004-009) and T flip-flop circuit ( para 0007),
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kitagawa with the teachings of Sakai having an edge detector that detects an edge of an input signal that indicates a voltage value corresponding to the current or the voltage of the power line and a T flip-flop circuit that inverts an output of the T flip-flop circuit each time the edge of the input signal is detected in order to creates a highly efficient, hardware-based frequency divider and status toggler.
Still, the combination does not disclose a T flip-flop circuit that inverts an output of the T flip-flop circuit, each time the edge of the input signal is detected.
Yet, the claim would have been obvious because a particularly well-known technique of employing inverter devices is recognized as part of the ordinary capabilities of one skilled in the art.
Regarding claim 9, the combination teaches an identification information receiving method executed by an identification information receiving device that receives identification information defined by a plurality of bits, the identification information being superimposed on a current or a voltage of a power line by an identification information transmitting device that is connected to the identification information receiving device via the power line, the identification information receiving method comprising: detecting an edge of an input signal that indicates a voltage value corresponding to the current or the voltage of the power line; and inverting an output that is defined by a binary signal, each time the edge of the input signal is detected (please see the rejection of claim 1).
Regarding claim 10, the combination teaches an identification information receiving program executed by an identification information receiving device that receives identification information defined by a plurality of bits, the identification information being superimposed on a current or a voltage of a power line by an identification information transmitting device that is connected to the identification information receiving device via the power line, the identification information receiving program causing a computer to execute: detecting an edge of an input signal that indicates a voltage value corresponding to the current or the voltage of the power line; and inverting an output that is defined by a binary signal, each time the edge of the input signal is detected (please see the rejection of claim 1).
Regarding claim 11, the combination teaches a non-transitory recording medium on which an identification information receiving program is written, the identification information receiving program being executed by an identification information receiving device that receives identification information defined by a plurality of bits, the identification information being superimposed on a current or a voltage of a power line by an identification information transmitting device that is connected to the identification information receiving device via the power line, the identification information receiving program causing a computer to execute: detecting an edge of an input signal that indicates a voltage value corresponding to the current or the voltage of the power line; and inverting an output that is defined by a binary signal, each time the edge of the input signal is detected (please see the rejection of claim 1).
Regarding claim 7, the combination teaches the identification information receiving device according to claim 1.
However, the combination does not explicitly state that when an authentication period that includes reception of the identification information ends, a power supply to an active element included in the edge detector is blocked.
Yet, the claim would have been obvious because the technique of adjusting authentication duration and achieving an action is part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of the technique for improvement in other situations.
Regarding claim 8, the combination teaches a removable and portable power storage pack that serves as the identification information receiving device according to claim 1 (see 50; Kitagawa).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kitagawa and Sakai as applied to claim 1 above, and further in view of Kawai (JP-2001358580-A).
Regarding claim 2, the combination teaches the identification information receiving device according to claim 1.
However does not disclose when an output signal of the T flip-flop circuit is at a low level after an edge detection period, a high-level signal is input to a clear terminal of the T flip-flop circuit and a low-level signal is input to a preset terminal of the T flip-flop circuit until a next edge detection period, and when the output signal of the T flip-flop circuit is at a high level after the edge detection period, a high-level signal is input to the preset terminal and a low-level signal is input to the clear terminal until the next edge detection period.
Yet, Kawai in the same field teaches an output signal of the T flip-flop circuit is at a low level after an edge detection period, a high-level signal is input to a clear terminal of the T flip-flop circuit and a low-level signal is input to a preset terminal of the T flip-flop circuit until a next edge detection period, and when the output signal of the T flip-flop circuit is at a high level after the edge detection period, a high-level signal is input to the preset terminal and a low-level signal is input to the clear terminal until the next edge detection period (see FIG. 5 shows an example of the configuration of the counter unit 14, which is composed of n (N=2n) T-FFs with clear & preset. The counter section 14 can be initialized to a predetermined counter value by performing a predetermined input to the clear/preset terminal of each T-FF, para 0038).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kitagawa and Sakai with the teachings of Kawai having an output signal of the T flip-flop circuit is at a low level after an edge detection period, a high-level signal is input to a clear terminal of the T flip-flop circuit and a low-level signal is input to a preset terminal of the T flip-flop circuit until a next edge detection period, and when the output signal of the T flip-flop circuit is at a high level after the edge detection period, a high-level signal is input to the preset terminal and a low-level signal is input to the clear terminal until the next edge detection period in order to guaranteed signal inversion and stable complementary level generation.
Allowable Subject Matter
Claims 2 and 5 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3 and 6 are dependent on claims 2 and 5 respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIM ORTIZ whose telephone number is (571)270-7114. The examiner can normally be reached 9:30am-6:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rexford Barnie can be reached at (571) 272-7492. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ELIM ORTIZ/Primary Examiner, Art Unit 2836
Prosecution Insights