DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/14/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al (pub # 20220262309).
Consider claim 1. Zhang et al teaches A pixel circuit, (Fig. 4 and paragraph 0094, pixel drive circuit). comprising a light-emitting element, (Fig. 4, OLED).
a drive circuit, (Fig. 4, Drive sub-circuit).
a light- emitting control circuit, (Fig. 4, Light-emitting control sub-circuit).
and a drive control circuit; (Fig. 4, Drive control sub-circuit).
wherein the light-emitting control circuit is electrically connected to a control node, (Fig. 4 and paragraph 0095, The light-emitting control sub-circuit is connected with the first node N1, the third node N3).
and is configured to control connection between the drive circuit and the light-emitting element or between the drive circuit and a power supply voltage terminal under control of a potential of the control node; (Fig. 4 and paragraph 0095, The drive sub-circuit is connected with the first node N1, the second node N2 and the third node N3 respectively. The light-emitting control sub-circuit is connected with the first node N1, the third node N3, a light-emitting signal line EM, a second power supply line VDD and a first electrode of a light-emitting element respectively, and configured to provide a signal of the second power supply line VDD to the first node N1 and a signal of the third node N3 to the first electrode of the light-emitting element under the control of a signal of the light-emitting signal line EM.).
wherein the drive circuit is electrically connected to a first node, (Fig. 4 and paragraph 0095, The drive sub-circuit is connected with the first node N1, the second node N2 and the third node N3 respectively).
and the drive circuit is configured to generate a drive current flowing from the power supply voltage terminal to the light-emitting element under control of a potential of the first node; (Fig. 4 and paragraph 0095, The drive sub-circuit is connected with the first node N1, the second node N2 and the third node N3 respectively, and configured to provide a drive current to the third node N3 under the control of signals from the first node N1 and the second node N2.).
and wherein the drive control circuit is electrically connected to the control node, (Fig. 4 and paragraph 0095, The drive control sub-circuit is connected with a first scanning signal line Gate1, a second scanning signal line Gate2, a data signal line Data, a second power supply line VDD, a second initial signal line Init2, a first node N1, a second node N2 and a third node N3 respectively).
a data line, (Fig. 4 and paragraph 0095, The drive control sub-circuit is connected with a first scanning signal line Gate1, a second scanning signal line Gate2, a data signal line Data).
an initial control terminal, (Fig. 4 and paragraph 0095, The drive control sub-circuit is connected with a first scanning signal line Gate1, a second scanning signal line Gate2, a data signal line Data, a second power supply line VDD, a second initial signal line Init2).
a light-emitting control terminal, Fig. 4 and paragraph 0095, The drive control sub-circuit is connected with a first scanning signal line Gate1).
and a light-emitting control voltage terminal, (Fig. 4 and paragraph 0095, The drive control sub-circuit is connected with a first scanning signal line Gate1, a second scanning signal line Gate2).
and is configured to control connection between the control node and the light-emitting control terminal or the light-emitting control voltage terminal according to a voltage signal provided by the data line under control of an initial control signal provided by the initial control terminal. (Fig. 4 and paragraph 0095, The drive control sub-circuit is connected with a first scanning signal line Gate1, a second scanning signal line Gate2, a data signal line Data, a second power supply line VDD, a second initial signal line Init2, a first node N1, a second node N2 and a third node N3 respectively, configured to provide a signal of the data signal line Data and a signal of the second node N2 to the first node N1 and the third node N3 respectively under the control of a signal of the first scanning signal line Gate1, and to provide a signal of the second initial signal line Init2 to the second node N2 under the control of a signal of the second scanning signal line Gate2.).
Consider claim 2. Zhang et al further teaches The pixel circuit according to claim 1, wherein a control terminal of the drive circuit is electrically connected to the first node, (Fig. 4 and paragraph 0095, The drive sub-circuit is connected with the first node N1, thus a control terminal of the drive sub-circuit is connected to the first node).
a first terminal of the drive circuit is electrically connected to the power supply voltage terminal, (Fig. 4 and paragraph 0095, The drive sub-circuit is connected with the first node N1, the second node N2 and the third node N3 respectively, and configured to provide a drive current to the third node N3 under the control of signals from the first node N1 and the second node N2. The light-emitting control sub-circuit is connected with the first node N1, the third node N3, a light-emitting signal line EM, a second power supply line VDD and a first electrode of a light-emitting element respectively, and configured to provide a signal of the second power supply line VDD to the first node N1).
and a second terminal of the drive circuit is electrically connected to a drive node, and the drive circuit is configured to generate a drive current flowing from the power supply voltage terminal to the drive node under control of the potential of the first node; (Fig. 4 and paragraph 0095, The drive sub-circuit is connected with the first node N1, the second node N2 and the third node N3 respectively, and configured to provide a drive current to the third node N3 under the control of signals from the first node N1 and the second node N2.).
wherein the light-emitting control circuit is further electrically connected to the drive node and a first electrode of the light-emitting element, (Fig. 4 and paragraph 0095, The light-emitting control sub-circuit is connected with the first node N1, the third node N3, a light-emitting signal line EM, a second power supply line VDD and a first electrode of a light-emitting element respectively).
and is configured to control connection between the drive node and the first electrode of the light-emitting element under control of the potential of the control node; (Fig. 4 and paragraph 0095, The light-emitting control sub-circuit is connected with the first node N1, the third node N3, a light-emitting signal line EM, a second power supply line VDD and a first electrode of a light-emitting element respectively, and configured to provide a signal of the second power supply line VDD to the first node N1 and a signal of the third node N3 to the first electrode of the light-emitting element under the control of a signal of the light-emitting signal line EM.).
and a second electrode of the light-emitting element is electrically connected to a first voltage terminal. (Fig. 4, second electrode of OLED is connected to VSS).
Consider claim 3. Zhang et al further teaches The pixel circuit according to claim 1, wherein a control terminal of the drive circuit is electrically connected to the first node, (Fig. 4 and paragraph 0095, The drive sub-circuit is connected with the first node N1, thus a control terminal of the drive sub-circuit is connected to the first node).
a first terminal of the drive circuit is electrically connected to a drive node, (Fig. 4 and paragraph 0095, The drive sub-circuit is connected with the first node N1, the second node N2 and the third node N3 respectively, and configured to provide a drive current to the third node N3 under the control of signals from the first node N1 and the second node N2.).
a second terminal of the drive circuit is electrically connected to a first voltage terminal, (Fig. 4 and paragraph 0095, The drive sub-circuit is connected with the first node N1, the second node N2 and the third node N3 respectively, and configured to provide a drive current to the third node N3 under the control of signals from the first node N1 and the second node N2. The light-emitting control sub-circuit is connected with the first node N1, the third node N3, a light-emitting signal line EM, a second power supply line VDD and a first electrode of a light-emitting element respectively, and configured to provide a signal of the second power supply line VDD to the first node N1).
and the drive circuit is configured to generate a drive current flowing from the drive node to the first voltage terminal under control of the potential of the first node; (Fig. 4 and paragraph 0095, The drive sub-circuit is connected with the first node N1, the second node N2 and the third node N3 respectively, and configured to provide a drive current to the third node N3 under the control of signals from the first node N1 and the second node N2.).
wherein a first electrode of the light-emitting element is electrically connected to the power supply voltage terminal; (Fig. 4, second electrode of OLED is connected to VSS).
and wherein the light-emitting control circuit is further electrically connected to a second electrode of the light-emitting element and the drive node, (Fig. 4 and paragraph 0095, The light-emitting control sub-circuit is connected with the first node N1, the third node N3, a light-emitting signal line EM, a second power supply line VDD and a first electrode of a light-emitting element respectively).
and is configured to control connection between the second electrode of the light-emitting element and the drive node under control of the potential of the control node. (Fig. 4 and paragraph 0095, The light-emitting control sub-circuit is connected with the first node N1, the third node N3, a light-emitting signal line EM, a second power supply line VDD and a first electrode of a light-emitting element respectively, and configured to provide a signal of the second power supply line VDD to the first node N1 and a signal of the third node N3 to the first electrode of the light-emitting element under the control of a signal of the light-emitting signal line EM.).
Consider claim 20. Zhang et al further teaches A display device, comprising the pixel circuit according to claim 1. (abstract).
Allowable Subject Matter
Claims 4-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Consider claim 4. The prior art of record does not teach or render obvious The pixel circuit according to claim 1,further comprising an energy storage circuit and a voltage control circuit; wherein a first terminal of the energy storage circuit is electrically connected to the first node, a second terminal of the energy storage circuit is electrically connected to a second node, and the energy storage circuit is configured to store electric energy; and wherein the voltage control circuit is electrically connected to the light-emitting control terminal, a second voltage terminal, and the second node, and is configured to control connection between the second voltage terminal and the second node under control of a light-emitting control signal provided by the light-emitting control terminal.
Claims 5-15 and 18-19 are objected to due to their dependency from claim 4.
Consider claim 16. The prior art of record does not teach or render obvious The pixel circuit according to claim 2, wherein the drive circuit comprises a drive transistor, and the light-emitting control circuit comprises a tenth transistor; wherein a gate electrode of the drive transistor is electrically connected to the first node, a first electrode of the drive transistor is electrically connected to the power supply voltage terminal, and a second electrode of the drive transistor is electrically connected to the drive node; and wherein a gate electrode of the tenth transistor is electrically connected to the light- emitting control terminal, a first electrode of the tenth transistor is electrically connected to the power supply voltage terminal, and a second electrode of the tenth transistor is electrically connected to the first electrode of the light-emitting element.
Consider claim 17. The prior art of record does not teach or render obvious The pixel circuit according to claim 3, wherein the drive circuit comprises a drive transistor, and the light-emitting control circuit comprises a tenth transistor; wherein a gate electrode of the drive transistor is electrically connected to the first node, a first electrode of the drive transistor is electrically connected to the drive node, and a second electrode of the drive transistor is electrically connected to the first voltage terminal; and wherein a gate electrode of the tenth transistor is electrically connected to the light- emitting control terminal, a first electrode of the tenth transistor is electrically connected to the second electrode of the light-emitting element, and a second electrode of the tenth transistor is electrically connected to the drive node.
Conclusion
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/CHAYCE R BIBBEE/Examiner, Art Unit 2624
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