DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Makino et al. (JP 2002-043756) in view of Nishiura et al. (JP 2008-034551).
Regarding claims 1-2, Makino discloses silicon nitride multilayer wiring board that has a metallized circuit layer with low resistance, and an excellent flat surface without warpage and breaking of wire (abstract). JP’756 disclose a silicon nitride multilayer wiring board (See Figure 2; [0019]):
PNG
media_image1.png
400
502
media_image1.png
Greyscale
comprises (2) a metallized (conductive) wiring layer (2) sandwiched between (1) insulation layers constituted by silicon nitride ceramic (See [0029]). JP’756 discloses that the metallized wiring layer (2) is formed from (4) tungsten-containing crystal phase, (5) a ceramic phase, and (6) pores (See [0020]). The metallized wiring layer of JP’756 extends in a planar direction inside the insulation layer.
However, Makino fails to disclose that the metallized wiring layer (corresponds to electrical conductor layer) comprising a metal phase and silica particles, and the metal phase surrounding the silica particles.
Whereas, Nishiura discloses a wiring board (1) comprises a conductor layer (2, wiring layer) in between insulating layers (1c and 1d) wherein the conductor layer (2) includes metal particles (2a) and glass powders (2b) (See Figure 1). The glass powders (2b) are mixed with metal particles (2a) and are isolated from each other (See Figure 1). The glass powder contains SiO2 (silica particles) (See unlabeled page 3, bottom of page). Nishiura discloses that the presences of glass in the conductor layer (2, wiring layer) reduces the difference in thermal expansion coefficient from the glass ceramic that constitutes the insulating base, and cause problems such as cracks and peeling at the interface between the conductor layer (2, wiring layer) and the insulating based (See unlabeled page 2, middle of page). Based from the figure 1, it is clear that metal phase surrounds the glass powders.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate silica powder (SiO2) of Nishiura into the conductor layer of JP’756, in order to reduce the difference in thermal expansion coefficient from the glass ceramic that constitutes the insulating base, and cause problems such as cracks and peeling at the interface between the conductor layer and the insulating based as suggested by Nishiura.
Regarding claim 3, with respect to L1/L10 in a range of 1.05 to 1.15, Change in size and shape is not patently distinct over the prior art absent persuasive evidence that the particular configuration of the claimed invention is significant. See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04[R-1].
Regarding claim 5, Makino discloses silicon nitride multilayer wiring board that has a metallized circuit layer with low resistance, and an excellent flat surface without warpage and breaking of wire (abstract). JP’756 disclose a silicon nitride multilayer wiring board (See Figure 2; [0019]): comprises (2) a metallized (conductive) wiring layer (2) sandwiched between (1) insulation layers constituted by silicon nitride ceramic (See [0029]). JP’756 discloses that the metallized wiring layer (2) is formed from (4) tungsten-containing crystal phase, (5) a ceramic phase, and (6) pores (See [0020]).
However, Makino fails to disclose that the crystalline metal phase comprises copper, silver or nickel as main component and each crystallite having a polygonal shape with a side that is linear, the crystallites being in contact with each other along the side of a grain boundary.
Whereas, Nishiura discloses a wiring board (1) comprises a conductor layer (2, wiring layer) in between insulating layers (1c and 1d) wherein the conductor layer (2) includes metal particles (2a) and glass powders (2b) (See Figure 1). The glass powders (2b) are mixed with metal particles (2a) and are isolated from each other (See Figure 1). The glass powder contains SiO2 (silica particles) (See unlabeled page 3, bottom of page). The copper, the silver and the gold, the copper is adopted desirably as the metal in the metal powder (page 5).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate metal such as copper or silver as taught by Nishiura in the conductor layer of Makino motivated by the desire to have superior conductivity.
With respect to each crystallite having a polygonal shape with a side that is linear, the crystallites being in contact with each other along the side of a grain boundary, Change in size and shape is not patently distinct over the prior art absent persuasive evidence that the particular configuration of the claimed invention is significant. See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04[R-1].
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Makino et al. (JP 2002-043756) in view of Nishiura et al. (JP 2008-034551) as applied to claim 1, further in view of (JP 3363369).
Regarding claim 2, Makino in view of Nishiura fails to disclose that the content of the silica particles is from 0.3-2.5 in a mass ratio, with the metal phase defined as 100.
Whereas, JP’369 discloses a metal body and a glass component containing a metal component and a glass component from both sides of a porcelain body formed by alternately laminating dielectric layers and internal electrode layers. In a multilayer ceramic capacitor in which an external electrode composed of one conductor layer, a second conductor layer containing a metal component and a resin component, and a third conductor layer made of a plated metal is formed, the first conductive layer is made of glass with respect to the metal component. The ingredients are 5-20% by weight, and the second conductive layer is made of resin with respect to the metal component (claim 1). JP’369 discloses multilayer ceramic capacitor, the first conductive layer contains 5 to 20% by weight of glass component to metal component (pages 2-3), whereas glass component corresponds to silica particles of the present invention.
The only deficiency of JP’369 is that JP’369 disclose the use of 5 wt% glass, while the present claims require 2.5 wt% silica.
It is apparent, however, that the instantly claimed amount of silica and that taught by JP’369 are so close to each other that the fact pattern is similar to the one in In re Woodruff , 919 F.2d 1575, USPQ2d 1934 (Fed. Cir. 1990) or Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed.Cir. 1985) where despite a “slight” difference in the ranges the court held that such a difference did not “render the claims patentable” or, alternatively, that “a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough so that one skilled in the art would have expected them to have the same properties”.
In light of the case law cited above and given that there is only a “slight” difference between the amount of glass component disclosed by JP’369and the amount disclosed in the present claims and further given the fact that no criticality is disclosed in the present invention with respect to the amount of silica, it therefore would have been obvious to one of ordinary skill in the art that the amount of silica disclosed in the present claims is but an obvious variant of the amounts disclosed in JP’369, and thereby one of ordinary skill in the art would have arrived at the claimed invention.
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Makino et al. (JP 2002-043756) in view of Nishiura et al. (JP 2008-034551) as applied to claim 1, further in view of Azuma et al. (US 2017/0068178).
Regarding claim 4, Makino in view of Nishiura fails to disclose that the silica particles have a diameter of 10-40 nm in a cumulative ratio of 70% or more.
Whereas, Azuma discloses multi-layer electrophotographic photosensitive member includes a conductive substrate and a photosensitive layer. The photosensitive layer includes a charge generating layer and a charge transport layer. The charge generating layer contains a charge generating material. The charge transport layer contains a charge transport material, a binder resin, and silica particles (abstract). The silica particles having an average particle diameter of 10-80 nm (claim 6).
It would have been obvious to one of ordinary skill in the art at the time the application was filed to form silica particles of Nishiura having a diameter of 10-80 nm as taught by Azuma in the conductor layer of Makino motivated by the desire to have improved abrasion resistance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RONAK C PATEL whose telephone number is (571)270-1142. The examiner can normally be reached M-F 8:30AM-6:30PM (FLEX).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALICIA CHEVALIER can be reached at 5712721490. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RONAK C PATEL/Primary Examiner, Art Unit 1788
Prosecution Insights