DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
1. Claim 32 is objected to because of the following informalities:
1.1. The claim-element/limitation relative to “a production device” (line 2) of claim 1 should be consistent and be written as “the production device” in order to improve consistency and clarity of the claim language because this claim-element/limitation already has antecedent basis on line-1 of claim-1.
2. Claim 49 is objected to because of the following informalities:
2.1. The claim-element/limitation relative to “a production device” (line 2) of claim 1 should be consistent and be written as “the production device” in order to improve consistency and clarity of the claim language because this claim-element/limitation already has antecedent basis on line-1 of claim-1.
3. Appropriate correction is required. The examiner appreciates the assistance of the Applicant(s).
Examiner’s Note
4. All the words in the language of the claims of which the specifications do not provide a definition in the form stated in the MPEP, the examiner has interpreted them by their plain meanings, pursuant to the MPEP 2111.01 “Plain Meaning” and MPEP 2173.01.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claim(s) 32-34 and 45 are/is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Love (Patent No.: US 5,477,160 hereinafter mentioned “Love”, which was submitted via IDS).
As per claim 32, Love discloses:
An environmental testing method (See MPEP 2111.02, Effect of Preamble, and II. Preamble Statements Reciting Purpose or Intended Use) for a production device (Figs. 1a and/or 1b, see the production-device/chip-carrier-under-test CUT 101. Also see column 4, lines 4-6) comprising:
attaching a production device (Figs. 1a and/or 1b, see the production-device/chip-carrier-under-test CUT 101. Also see column 4, lines 4-6) to a board (Figs. 1a and/or 1b, see the board/MTC 102 formed by substrate 103 and chips 104. Also see column 4, lines 18-25); and
performing environmental testing on one or more of the production device or board (see column 15, lines 8-14; and/or abstract),
wherein the environmental testing comprises one or more of thermal, mechanical, or pressure testing (column 14, lines 66-67 to column 15, lines 1-7).
As per claim 33, Love discloses the method of claim 32 as described above.
Love further discloses:
wherein the board comprises a plurality of test points (Fig. 1a, see the substrate 103 of the board/MTC 102 with a plurality of test-points/connector-bond-pads 108. Also see column 5, lines 1-4) arranged such that attaching the production device to the board (Figs. 1a and/or 1b, see the production-device/chip-carrier-under-test CUT 101 and the board/MTC 102 formed. Also see column 4, lines 4-6 and lines 18-25) provides an electrical connection between external connectors of the production device (Fig. 1a, see the external-connectors/bond-pads 113 of the production-device/CUT 101. Also see column 4, lines 54-59) and the test points (Fig. 1a, the plurality of test-points/connector-bond-pads 108. Also see column 5, lines 1-4).
As per claim 34, Love discloses the method of claim 32 as described above.
Love further discloses:
evaluating one or more electrical or mechanical connections (see column 12, lines 8-41) between the production device and the board (Figs. 1a and/or 1b, see the production-device/ CUT 101 and the board/MTC 102. Also see column 4, lines 4-6 and lines 18-25).
As per claim 45, Love discloses the method of claim 32 as described above.
Love further discloses:
wherein the attaching comprises applying force to the production device to secure it to a testing structure of the board (Figs. 1a and/or 1b, see the production-device/ CUT 101 and the board/MTC 102. Also see column 4, lines 4-6 and lines 18-25).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim(s) 35 and 38-47 are/is rejected under 35 U.S.C. 103 as being unpatentable over Love.
As per claim 35, Love discloses the method of claim 34 as described above.
Love further discloses:
wherein the evaluating one or more connections comprises testing a signal path (Fig. 7, see the any of the paths 704 and/or 705. Also see column 5, lines 49-50) between at least one test point (Fig. 1a, see the test-points/connectors 108. Also see column 5, lines 1-4) and the production device (Fig. 7, see the production-device/carrier-under-test 701. Also see column 5, lines 49-53).
As per claim 38, Love discloses the method of claim 34 as described above.
Love further discloses:
applying power to the production device (Fig. 10, see the production-device/CUT 1001. Also see column 6, lines 14-21; and column 7, lines 6-9).
As per claim 39, Love discloses the method of claim 38 as described above.
Love further discloses:
evaluating performance of the production device (see column 15, lines 4-7, and/or, column 7, lines 39-45).
As per claim 40, Love discloses the method of claim 38 as described above.
Love further discloses:
wherein the power is applied using one or more test points of the board (Fig. 10, see the plurality of test-points/connectors 1008 of the board/test-substrate 1003 where power is provided. Also see column 7, lines 6-9).
As per claim 41, Love discloses the method of claim 38 as described above.
Love further discloses:
measuring a signal generated in the production device (Fig. 10, see the signal(s) generated by production-device/carrier-under-test 1001. Also see column 7, lines 39-45),
wherein the signal is measured using one or more test points of the board (Fig. 10, see the plurality of test-points/connectors 1008 of the board/test-substrate 1003 where power is provided. Also see column 7, lines 6-9).
As per claim 42, Love discloses the method of claim 39 as described above.
Love further discloses:
wherein the production device is designed for a particular function (Fig. 10, see any implicit function of the production-device/carrier-under-test 1001. Also see column 7, lines 39-45), and the evaluating comprises testing performance of that function (see column 15, lines 4-7, and/or, column 7, lines 39-45).
As per claim 43, Love discloses the method of claim 32 as described above.
Love further discloses:
wherein the board is a test board comprising a substrate (Fig. 1a, see the test-substrate 103 of the board/MTC 102 with a plurality of test-points/connector-bond-pads 108. Also see column 5, lines 1-4);
a plurality of connection pads (Fig. 1a, see the bond-pads 106. Also see column 4, lines 54-59); and
a plurality of test points (Fig. 1a, see the test-points/connector-bond-pads 108. Also see column 5, lines 1-4) arranged for one or more of: (i) measurement of an electrical connection (see column 12, lines 34-41) between the board and the production device (Fig. 1a, see the board/MTC 102 and production-device/chip-carrier-under-test CUT 101. Also see column 5, lines 1-4; and/or column 4, lines 4-6); or (ii) measurement of a signal (see column 7, lines 39-45) or function of the production device mounted on the board (see column 15, lines 4-7).
As per claim 44, Love discloses the method of claim 32 as described above.
Love further discloses:
wherein the board is a breakout board (Figs. 1a and/or 1b, see the board/MTC 102 is formed by substrate 3 that is a breakout-board/printed-circuit-board. Also see column 4, lines 18-32) comprising one or more additional components mounted thereon (Figs. 1a and/or 1b, see the additional-component/tester 105. Also see column 4, lines 22-28), and wherein the additional components comprise one or more of:
(i) a micro-SD card;
(ii) a micro-USB port;
(iii) a power or communications port;
(iv) a JTAG port;
(v) boot/EPROM memory for configuration of the production device (Also see column 4, lines 22-28);
(vi) test pin adapters;
(vii) a reset button;
(viii) LEDs;
(ix) an l2C port;
(x) an oscillator; or
(xi) one or more filters.
As per claim 45, Love discloses the method of claim 32 as described above.
Love further discloses:
wherein the attaching comprises applying force to the production device to secure it to a testing structure of the board (Also see column 4, lines 38-43. The attaching force is implicit when the substrate is moved to be attached to the carrier under test).
As per claim 46, Love discloses the method of claim 32 as described above.
Love further discloses:
wherein the attaching comprises performing a temporary mounting with non-permanent electrical and mechanical connections between the production device and the board (Fig. 5, see the production-device/chip-carrier-under-test CUT 501 and the substrate 502 formed with an elastomeric sheet/film that is mechanical connected in the non-conductive x and y directions and electrical-conductive connected in the z direction . Also see column 13, lines 14-20).
As per claim 47, Love discloses the method of claim 46 as described above.
Love further discloses:
wherein the board comprises a testing structure having at least one socket, and
wherein the attaching comprises applying force to the production device to secure it to the at least one socket.
7. Claim(s) 36 and 37 are/is rejected under 35 U.S.C. 103 as being unpatentable over Love in view of Dibish et al. (Patent No.: US 6,507,205 hereinafter mentioned as “Dibish”).
As per claim 36, Love discloses the method of claim 35 as described above.
Love discloses the test points and corresponding external connectors but does not explicitly disclose:
using or producing a list that maps said test points and said corresponding external connectors of said production device.
However, Dibish further discloses:
using or producing a list that maps test points and corresponding external connectors of the production device (see column 2, lines 16-26. The test-points of the Kwon is the point of attachment of each DUT that connects to the socket with corresponding cable connector pins).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the feature relative to “using or producing a list that maps said test points and said corresponding external connectors of said production device”, as it is disclosed by Dibish into Love, with the motivation and expected benefit related to improving the system, method and measurements by mapping the proper connection of signals between the DUT socket and the tester cables (Dibish, Column 2, Lines 24-26) while also providing a unique mapping exists for each combination of IC design and package type (Dibish, Column 3, Lines 57-59).
Furthermore, Love states that “A description of the particular embodiment is given above for the understanding of the present invention. It will be understood by those skilled in the art that various modifications and additions can be made without substantially departing from the scope of this invention” (Love, Column 15, Lines 14-19).
Furthermore, Dibish states that “The above description of the invention is intended to be illustrative and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure” (Dibish, Column 4, Lines 26-30).
As per claim 47, Love discloses the method of claim 46 as described above but does not explicitly disclose at least one socket.
However, Dibish further discloses:
wherein the board comprises a testing structure having at least one socket (see column 2, lines 16-26. The PCB has a socket for the DUT), and
wherein the attaching comprises applying force to the production device to secure it to the at least one socket (see column 2, lines 16-26. This is implicit at the time of placing the DUT in the socket).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the feature relative to “at least one socket”, as it is disclosed by Dibish into Love, with the motivation and expected benefit related to improving the system, method and measurements by receiving and holding a plurality of the DUTs (Dibish, Column 2, Lines 44-46), and also mapping the proper connection of signals between the DUT socket and the tester cables (Dibish, Column 2, Lines 24-26) while also providing a unique mapping exists for each combination of IC design and package type (Dibish, Column 3, Lines 57-59).
8. Claim(s) 37 are/is rejected under 35 U.S.C. 103 as being unpatentable over Love in view of Dibish, and further in view KWON et al. (Pub. No.: US 2021/0141014 hereinafter mentioned as “Kwon”, which was submitted via IDS).
As per claim 37, the combination of Love and Dibish discloses the method of claim 36 as described above but does not explicitly disclose:
wherein the list further comprises an identifier associated with the test point, external connector, or path type.
However, Kwon further discloses:
wherein the list further comprises an identifier associated with the test point, external connector, or path type (see [0116]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the feature relative to “wherein the list further comprises an identifier associated with the test point, external connector, or path type”, as it is disclosed by Kwon into Love in view of Dibish, with the motivation and expected benefit related to improving the system, method and measurements by designating the same die identifier to the same die in the plurality of the semiconductor packages under test PUT and the die database (Kwon, Paragraph [0116]) while also determining a vertical point of the fault and to determine a fault die having the fault (Kwon, Paragraph [0010]).
9. Claim(s) 48-50 are/is rejected under 35 U.S.C. 103 as being unpatentable over Love in view of Whetsel, Lee D. (Pub. No.: EP 0852354 hereinafter mentioned as “Lee”, which was submitted via IDS).
As per claim 48, Love discloses the method of claim 32 as described above.
Love further discloses:
wherein the board (Figs. 1a and/or 1b, see the board/MTC 102 formed by substrate 103 and chips 104. Also see column 4, lines 18-25) comprises a mounting assembly containing a plurality of connection pads (Fig. 1a, see the bond-pads 106. Also see column 4, lines 54-59) arranged for mounting thereon the production device (Figs. 1a and/or 1b, see the production-device/chip-carrier-under-test CUT 101. Also see column 4, lines 4-6).
Love does not explicitly disclose:
a plurality of test pads individually interconnected with one of each of said plurality of connection pads.
However, Lee further discloses:
a plurality of test pads individually interconnected with one of each of said plurality of connection pads (Figs. 4, 9A and/or 26A, see at least pad 256 interconnected with pad 65 for testing. Also see column 1, lines 12-27; column 6, lines 34-41; and/or column 18, lines 31-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the feature relative to the “plurality of test pads individually interconnected with one of each of said plurality of connection pads”, as it is disclosed by Lee into Love, with the motivation and expected benefit related to improving the system, method and measurements by providing a bond pad arrangement that maximizes bond pad access to the signal collectors (Lee, Column 2, Lines 11-12).
As per claim 49, Love discloses:
A system for environmental testing (See MPEP 2111.02, Effect of Preamble, and II. Preamble Statements Reciting Purpose or Intended Use) of a production device (Figs. 1a and/or 1b, see the production-device/chip-carrier-under-test CUT 101. Also see column 4, lines 4-6), comprising:
a production device (Figs. 1a and/or 1b, see the production-device/chip-carrier-under-test CUT 101. Also see column 4, lines 4-6);
a test board (Figs. 1a and/or 1b, see the board/MTC 102 formed by substrate 103 and chips 104. Also see column 4, lines 18-25) having a mounting assembly containing a plurality of connection pads (Fig. 1a, see the bond-pads 106. Also see column 4, lines 54-59) arranged for mounting thereon the production device (Figs. 1a and/or 1b, see the production-device/chip-carrier-under-test CUT 101. Also see column 4, lines 4-6), wherein said test board is adapted for environmental testing (see column 15, lines 8-14; and/or abstract);
wherein the production device comprises a plurality of external connectors (Fig. 1a, see the external-connectors/bond-pads 113 of the production-device/CUT 101. Also see column 4, lines 54-59) mounted to the plurality of connection pads (Fig. 1a, see the bond-pads 106. Also see column 4, lines 54-59) of the test board (Fig. 1a, see the test-substrate 103 of the board/MTC 102 with a plurality of test-points/connector-bond-pads 108. Also see column 5, lines 1-4) for testing the connections between the connection pads and the external connectors of the production device (see column 12, lines 38-44. The verification of signal paths between carrier with external pads and the test chip that that are connected to the connection pads of the board) while performing environmentally tests (see column 15, lines 8-14; and/or abstract).
Love does not explicitly disclose:
wherein said production device is a packaged electrical device; and
a plurality of test pads individually interconnected with one of each of said plurality of connection pads.
However, Lee further discloses:
wherein the production device is a packaged electrical device (Figs. 3 and/or 3A, see the production device being tested after the IC is packaged. Also see column 6, lines 9-11; and/or column 20, lines 2-11); and
a plurality of test pads individually interconnected with one of each of said plurality of connection pads (Figs. 4, 9A and/or 26A, see at least pad 256 interconnected with pad 65 for testing. Also see column 1, lines 12-27; column 6, lines 34-41; and/or column 18, lines 31-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the feature relative to the “wherein said production device is a packaged electrical device; and plurality of test pads individually interconnected with one of each of said plurality of connection pads”, as it is disclosed by Lee into Love, with the motivation and expected benefit related to improving the system, method and measurements by providing a bond pad arrangement that maximizes bond pad access to the signal collectors (Lee, Column 2, Lines 11-12).
As per claim 50, Love discloses the system of claim 49 as described above.
Love further discloses:
wherein the production device is mounted to the test board with non-permanent electrical and mechanical connections between the production device and the test board (Fig. 5, see the production-device/chip-carrier-under-test CUT 501 and the substrate 502 formed with an elastomeric sheet/film that is mechanical connected in the non-conductive x and y directions and electrical-conductive connected in the z direction . Also see column 13, lines 14-20).
10. Claim(s) 51 are/is rejected under 35 U.S.C. 103 as being unpatentable over Love in view of Lee, and further in view of Kwon.
As per claim 51, Love discloses the system of claim 49 as described above.
Love further discloses:
an external controller (Figs. 1a and/or 1b, see the external-controller/tester 105. Also see column 4, lines 22-28) mounted on the test board (Figs. 1a and/or 1b, see the board/MTC 102 is formed by substrate 3. Also see column 4, lines 18-32), wherein the controller is adapted to be electrically powered and connected to the production device under test (Fig. 1a, see the board/MTC 102 and production-device/chip-carrier-under-test CUT 101. Also see column 5, lines 1-4; and/or column 4, lines 4-6);
a memory device, wherein the memory device (Fig. 1a, see the memory 130. Also see column 4, lines 22-28) is adapted to be electrically powered and connected to the production device under test (Fig. 1a, see the board/MTC 102 and production-device/chip-carrier-under-test CUT 101. Also see column 5, lines 1-4; and/or column 4, lines 4-6).
Love in view of Lee does not explicitly disclose:
a communication device, wherein the communication device is adapted to be electrically powered and interconnected between the production device under test and an external controller.
However, Kwon further discloses:
a communication device, wherein the communication device (Fig. 1, see the communication-device/test-controller 400. Also see [0030]) is adapted to be electrically powered and interconnected between the production device under test (Fig. 1, the production-device-under-test/PUT of securing assembly 120. Also see [0030] and [0039]) and an external controller (Fig. 1, see the external-controller/tester 200. Also see [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the feature relative to the “communication device, wherein the communication device is adapted to be electrically powered and interconnected between the production device under test and an external controller”, as it is disclosed by Kwon into Love in view of Lee, with the motivation and expected benefit related to improving the system, method and measurements by providing a test apparatus for testing semiconductor packages in which the operation test and the fault detection are conducted in the same test chamber for reducing the feedback time (Kwon, Paragraph [0007]).
Furthermore, pursuant to MPEP 2144.04 Legal Precedent as Source of Supporting Rationale, VI. REVERSAL, DUPLICATION, OR REARRANGEMENT OF PARTS, the Rearranging/shifting the position of the components with respect to each other does not modify the operation of the testing system in a novel manner, therefore, components’ positions and/or rearrangement has no patentable weight (see “In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950)). Additionally, rearranging the component positions is an obvious design choice (see “In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVARO E. FORTICH whose telephone number is (571) 272-0944. The examiner can normally be reached on Monday thru Friday from 8:30am to 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Huy Phan, can be reached on (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVARO E FORTICH/Primary Examiner, Art Unit 2858
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