DETAILED ACTION
Response to Arguments
Applicant’s arguments, see pages 1 and 2 of the Remarks, filed on May 14, 2026, with respect to drawing objections have been fully considered and are persuasive. The objection of the drawings has been withdrawn.
Applicant’s arguments, see page 2 of the Remarks, filed on May 14, 2026, with respect to claim objections have been fully considered and are persuasive. The objection of claims 3-6 and 8-11 has been withdrawn.
Applicant’s arguments, see pages 3-6 of the Remarks, filed on May 14, 2026, with respect to the rejection(s) of claims 1-5, 7, 8, and 10 under 35 U.S.C. §102(a)(2) and claim 6 under 35 U.S.C. §103 (claims 5 and 6 have been canceled) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chung (US 6,998,882 B1).
Drawings
The drawings were received on May 14, 2026. These drawings are acceptable by the examiner.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4, 7-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Gagnon et al. (US 9,819,544 B2), hereinafter “Gagnon” in view of Chung (US 6998882 B1), hereinafter “Chung”.
Gagnon illustrates a communication system 300 in FIG. 2 comprising a master device and daisy-chained devices (310-340) for use in a daisy chain communication configuration.
FIG. 3 illustrates components of a daisy-chained device 1 or I of FIG. 2 comprising processing functionality 331 and signal transmission functionality 335, wherein the signal transmission functionality 335 comprises an input terminal 336 receives an input signal from an output terminal 200 of the master device, a frequency divider 337, and an output terminal 338, and wherein the processing functionality 331 comprises a communication interface 333 connected to the master device via a communication link 230, a processing unit 332 processes the input signal from the input terminal 336, and a memory 334 including an address lookup table 220.
Regarding claim 1, Gagnon illustrates a terminal device (daisy-chained device I in FIG. 3) for which a communication address (a plurality of addresses and corresponding frequencies) is set, the terminal device comprising: an input terminal (input terminal 336) to which a pulse repetition signal (the input signal having a pre-determined base frequency or a square wave which is considered a specific type of pulse repetition signal. In signal processing, the rate at which these waves repeat is known as the pulse repetition frequency (PRF) or pulse repetition rate (PRR), which is synonymous with the fundamental frequency of the periodic signal. Col. 5, lines 26-32) for setting the communication address is input; a signal converter (frequency divider 337)
However, Gagnon fails to show or teach that the frequency divider 337 functions as a signal converter that converts a duty ratio of the pulse repetition signal input to the input terminal and outputs a converted pulse repetition signal.
Chung illustrates a frequency divider 20 in FIG. 4 includes a reference-frequency generator 22, a bit shifter 24, comparators 26 and 28, a counter 30, a JK flip flop 32, an AND gate 34, a D flip flop 36, an inverter (NOT gate) 38, and an OR gate 40.
Chung also teaches that the frequency divider 20 is configured to generate odd-number and even-number divided frequencies with a 50% duty cycle (Col. 1, lines 7-10). In other words, a frequency divider that takes an incoming pulse signal and forces the output to have a strict 50% duty cycle regardless of whether it divides by an odd or even integer must mathematically and physically change the duty ratio of that incoming signal (unless the input was already exactly 50% and no division occurred). Because the output structure inherently forces a 50% duty ratio, it is automatically a “signal converter that converts a duty ratio.”
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art as taught by Chung to implement Gagnon’s frequency divider 337 with Chung’s frequency divider of the daisy-chained device to achieve a perfect 50% duty cycle for both even and odd division ratios of the pulse repetition signal in order to synchronize directly with source clock edges of edge tracking, introduce less phase noise than analog converters of low jitters, and reduce the fluctuations of the distort of the output duty cycle.
Regarding claim 2, as shown in FIG. 3, the daisy-chained device further comprising an information processing part (processing unit 332) that sets the communication address based on the frequency or the duty ratio of the pulse repetition signal input to the input terminal.
Regarding claim 3, as shown in FIG. 3, the daisy-chained device further comprising a storage (address lookup table 220 of the memory 334) in which a correspondence relationship between the frequency or the duty ratio of the pulse repetition signal and the communication address is stored in advance, wherein the information processing part sets the communication address based on the frequency or the duty ratio of the pulse repetition signal input to the input terminal and the correspondence relationship stored in the storage. Also see col. 6, line 60 to col. 7, line 3.
Regarding claim 4, as shown in FIG. 3, wherein the address lookup table 220 of the memory 334 stores the communication address set by the processing unit 332. Although Gagnon does not explicitly show or teach that the communication address is held in the address lookup table 220 of the memory 334 after the daisy-chained device is powered off, it is well known in the art that a processing circuit, such as the processing unit 332 and the address lookup table 220 of the memory 334 of the processing functionality 331 often utilizes non-volatile memory, such as read only memory (ROM), flash memory (NAND/NOR), or non-volatile random access memory (NVRAM), clearly, as shown in FIG. 3, the processing unit 332 and the memory-based LUT 334 are standard components in computing and networking, the persistence of data after power-off is determined by the choice between volatile and non-volatile memory for the address lookup table 220 to store addresses or frequencies that can be retrieved via direct addressing, replacing the need for expensive runtime re-calculations.
Regarding claim 7, as shown in FIG. 3, the daisy-chained device further comprising a bus communication terminal (the communication interface 333) different from the input terminal 336 and the output terminal 338, wherein a control signal (from the processing unit 332) for controlling the terminal device is input to the bus communication terminal, and the control signal includes information related to the communication address set by the information processing part (the communication interface 333 and the address lookup table 220).
Regarding claim 8, as shown in FIG. 2, the communication system (300) comprising: a plurality of terminal devices (daisy-chained devices 310-340) each of which is the terminal device (FIG. 3); and a management device (master device) that outputs the pulse repetition signal (200), wherein the plurality of terminal devices include at least a first terminal device (310), a second terminal device (320), and a third terminal device (330), the management device is connected to the input terminal of the first terminal device, the output terminal of the first terminal device is connected to the input terminal of the second terminal device, and the output terminal of the second terminal device is connected to the input terminal of the third terminal device.
Regarding claim 10, as applied to claim 8 and shown in FIG. 2, wherein each of the plurality of terminal devices is bus-connected to the management device via a bus communication terminal (the communication interface 306 or 333, such as a universal serial bus USB interface, col. 7, lines 4-10) different from the input terminal 336 and the output terminal 338, the management device controls each of the plurality of terminal devices by outputting a control signal (from the processing unit 302) for controlling each of the plurality of terminal devices to the bus communication terminal, and the control signal includes information related to the communication address set by each of the plurality of terminal devices.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. relates to a frequency divider with duty cycle adjustment within a feedback loop. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in the feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Young T. Tse whose telephone number is (571)272-3051. The examiner can normally be reached Mon-Fri 10:30am-7pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh M Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Young T. Tse/Primary Examiner, Art Unit 2632
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