DETAILED ACTION
This Office action is in response to the application filed on 21 November 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,2,3,10 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jun Li et. al (2009 Twenty-Fourth Annual IEEE Applied Power Electronics Conference and Exposition; hereafter “Li”).
-Regarding claim 1:
Li discloses:
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A method for driving an active neutral point clamped (ANPC} circuit (Figure 1) of a converter, comprising: determining an output state switching sequence of the ANPC circuit (Table I,II, III), aiming at an inner transistor (Fig. 1; Sa2, 3, sb2,3, and Sc2,3) and an outer transistor (Fig. 1; Sa1, 4, sb1,4, and Sc1,4) among switching transistors in the ANPC circuit of the converter bearing a switching loss within two half switching cycles of a switching cycle (I would say that all of the transistors that are turned on or off during the switching cycle will bear a switching loss, and it is well-within the skill of the person of ordinary skill in the art ; paragraph I; “It uses active neutral-point clamped switches in traditional three-level NPC inverter to solve the inherent drawback of NPC topology – unbalanced loss distribution among the switching devices.”), respectively; and generating control signals for the switching transistors (paragraph III A; “Therefore, the reference signal and carrier signals need not change, and the output voltage is not reduced.” and “using phase voltage as three-phase symmetrical reference signals, the line-to-line voltage should be used.”) in the ANPC circuit based on the output state switching sequence, and outputting the control signals (table I,II,III).
-Regarding claim 2:
Li discloses:
The method for driving an ANPC circuit of a converter according to claim 1, wherein the determining an output state switching sequence of the ANPC circuit (Table I,II, III), aiming at an inner transistor (Fig. 1; Sa2, 3, sb2,3, and Sc2,3) and an outer transistor (Fig. 1; Sa1, 4, sb1,4, and Sc1,4) among switching transistors in the ANPC circuit of the converter bearing a switching loss within two half switching cycles of a switching cycle (I would say that all of the transistors that are turned on or off during the switching cycle will bear a switching loss, and it is well-within the skill of the person of ordinary skill in the art. ; paragraph I; “It uses active neutral-point clamped switches in traditional three-level NPC inverter to solve the inherent drawback of NPC topology – unbalanced loss distribution among the switching devices.”), respectively comprises: determining zero-level output states of the output state switching sequence within the two half switching cycles of the switching cycle (Table I; switching state) of the ANPC circuit, the zero-level output states comprising a first zero-level output state in which the inner transistor bears the switching loss and a second zero-level output state in which the outer transistor bears the switching loss (Table I; switching state).
-Regarding claim 3:
Li discloses:
The method for driving an ANPC circuit of a converter according to the method for driving an ANPC circuit of a converter according to wherein before the determining an output state switching sequence of the ANPC circuit, the method further comprises: combining with an objective of balancing an on-state loss borne by the inner transistor (table II; on-off sequence of Sa2, 3, ; paragraph I; “It uses active neutral-point clamped switches in traditional three-level NPC inverter to solve the inherent drawback of NPC topology – unbalanced loss distribution among the switching devices.”).
-Regarding claim 10:
Li discloses:
The method for driving an ANPC circuit of a converter according to claim 1,wherein the generating control signals for switching transistors in the ANPC circuit based on the output state switching sequence (paragraph III A; “Therefore, the reference signal and carrier signals need not change, and the output voltage is not reduced.” and “using phase voltage as three-phase symmetrical reference signals, the line-to-line voltage should be used.”, table I,II,III), and outputting the control signals comprises: generating, for each of the switching transistors in the ANPC circuit, the control signal for the switching transistor based on on-off states of the switching transistor in the respective output states in the output state switching sequence (table I,II,III), and outputting the control signals; or generating, for each of the switching transistors in the ANPC circuit, the control signal for the switching transistor by comparing with a carrier wave (paragraph III; “ the reference signal and carrier signals need not change, and the output voltage is not reduced.”), aiming at achieving the output state switching sequence, and outputting the control signals.
-Regarding claim 12:
Li discloses:
The converter according to claim 11, wherein a quantity of the switching transistors in the ANPC circuit is six (Fig. 1; Sa1-6 at each ANPC), wherein a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor among the six switching transistors are connected in series in sequence (Fig. 1; Sa1-4); a terminal of the first switching transistor is connected to a positive electrode of a direct- current side of the ANPC circuit (Fig. 1; Sa1), and a terminal of the fourth switching transistor is connected to a negative electrode of the direct-current side of the ANPC circuit (Fig. 1; Sa4); the first switching transistor and the fourth switching transistor serve as two outer transistors (Fig. 1; Sa1, Sa4) of the ANPC circuit; a connection point of the second switching transistor and the third switching transistor is connected to an alternating-current side (Fig. 1; node A) of the ANPC circuit; and the second switching transistor and the third switching transistor serve as two inner transistors (Fig. 1; Sa2 , Sa3) of the ANPC circuit; and a connection point of the first switching transistor and the second switching transistor is connected to a neutral point of the direct-current side of the ANPC circuit via a fifth switching transistor (Fig. 1; Sa1, 2, 5 and node o); a connection point of the third switching transistor and the fourth switching transistor is connected to the neutral point of the direct-current side of the ANPC circuit via a sixth switching transistor (Fig. 1; Sa3, 4, 6 and node o); and the fifth switching transistor and the sixth switching transistor serve as two clamping transistors (Fig. 1; Sa5, Sa6) of the ANPC circuit.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jun Li et. al (2009 Twenty-Fourth Annual IEEE Applied Power Electronics Conference and Exposition; hereafter “Li”) in view of Ryota Asakura et. al (US20250202384A1; hereafter “Ryota”).
-Regarding claim 11:
Li discloses:
A converter, comprising: a main circuit; and a controller; wherein the main circuit comprises at least one active neutral point clamped (ANPC) circuit (Fig. 1; three ANPC circuits);
However, Li does not disclose a controller for the multiple ANPC circuits.
Ryota, in the same field of endeavor, discloses:
“and the main circuit is controlled by the controller (Fig. 1; controller), and the controller is configured to perform the method for driving an ANPC circuit”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Li such that a commonly used switching circuit controller described in Ryota is applied to the three-level ANPC converter. Doing so allows for improving control of switching transistors in the three-level ANPC converter.
-Regarding claim 13:
Ryota discloses:
The converter according to claim 11, wherein a quantity of the ANPC circuit in the main circuit is three (Fig. 1; 21,22,23); and direct-current sides of the ANPC circuits are connected in parallel (Fig. 1; parallel connection to DC source) to each other, and the alternating-current side of each of the ANPC circuits serves as a phase of an alternating-current side (Fig. 1; U,V,W phase of Load) of the main circuit.
Allowable Subject Matter
Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
The following is a statement of reasons for the indication of allowable subject matter:
-with respect to claim 4:
the prior art in Li discloses the claimed invention in basic claim but do not further disclose about a third zero-level output state in which a phase current flows into or flows out of a bridge arm through two parallel-connected branches.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEUNG HO CHOI whose telephone number is (571)272-8188. The examiner can normally be reached Monday-Thursday, 7:30 AM - 5:30 PM ET.
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/SEUNG HO CHOI/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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