Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 12-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eigo et al. (JP Patent # 2011061439A).
[Claim 1]
An information processing device comprising a sensor that acquires image generation data (camera 21, Paragraph 21); and
a conversion circuit (111, fig. 1) that converts the image generation data based on a predetermined interface or data format acquired by the sensor into image generation data based on another interface or data format compatible with a processor (Paragraph 27, The image acquisition unit 111 uses the data format determination function 1111 to detect and determine the physical wiring from the imaging device 20 based on, for example, voltage fluctuation of the I / O pin of the connector 114 and the image acquisition part 111 determines the data format of the image data from the imaging device 20 from the voltage fluctuation period input into an I / O pin and Paragraph 28, The image acquisition unit 111 receives image data from the imaging device 20 via the connector 114, and converts the data format of the image data by the data format conversion function 1112. The image acquisition unit 111 outputs the image data after the data format conversion to the image processing unit 12 at a bit rate based on the clock signal generated by the crystal oscillator 113).
[Claim 2]
The information processing device according to claim 1, further comprising the processor (12) that processes the image generation data converted by the conversion circuit (Paragraph 25, The conversion circuit is a circuit for converting the data format of the image data from the imaging device 20 into a uniform data format to be processed by the image processing unit 12).
[Claim 3]
The information processing device according to claim 2, wherein the conversion circuit is a circuit in which logic is rewritable (Paragraph 26, The image acquisition unit 111 configures a logic circuit on the FPGA (FPGAs are field programmable gate arrays that are programmable or rewritable) based on circuit information stored in the nonvolatile memory 112. That is, the image acquisition unit 111 has a data format determination function 1111 based on circuit information 1121 and a data format conversion function 1112 based on circuit information 1122-1 to 1122-n), and the processor rewrites the logic according to a type of the sensor (The image acquisition unit 111 configures a logic circuit on the FPGA (FPGAs are field programmable gate arrays that are programmable or rewritable) based on circuit information and the circuit information will be different for different types of sensors).
[Claim 4]
The information processing device according to claim 3, further comprising a memory that stores rewrite information for rewriting the logic (Paragraph 26, The image acquisition unit 111 configures a logic circuit on the FPGA based on circuit information stored in the nonvolatile memory 112. That is, the image acquisition unit 111 has a data format determination function 1111 based on circuit information 1121 and a data format conversion function 1112 based on circuit information 1122-1 to 1122-n), wherein the processor rewrites the logic based on the rewrite information.
[Claim 5]
The information processing device according to claim 1, further comprising a memory that stores configuration information regarding the sensor and the conversion circuit (Paragraph 24, The image acquisition unit 111 is a device in which a hardware circuit can be reconfigured, such as an FPGA (Field Programmable Gate Array), CPLK (Complex Programmable Logic Device), or PLD (Programmable Logic Device). Circuit information used at the time of reconfiguration is stored in the nonvolatile memory 112 in advance. The nonvolatile memory 112 stores circuit information 1121 related to the determination circuit and circuit information 1122-1 to 1122-n related to the conversion circuit. The discriminating circuit is a circuit that discriminates the data format of the image data from the imaging device 20. Here, the data format is, for example, a so-called VGA).
[Claim 12]
An information processing system comprising a sensor that acquires image generation data (camera 21, Paragraph 21); and
a conversion circuit (111, fig. 1) that converts the image generation data based on a predetermined interface or data format acquired by the sensor into image generation data based on another interface or data format compatible with a processor (Paragraph 27, The image acquisition unit 111 uses the data format determination function 1111 to detect and determine the physical wiring from the imaging device 20 based on, for example, voltage fluctuation of the I / O pin of the connector 114 and the image acquisition part 111 determines the data format of the image data from the imaging device 20 from the voltage fluctuation period input into an I / O pin and Paragraph 28, The image acquisition unit 111 receives image data from the imaging device 20 via the connector 114, and converts the data format of the image data by the data format conversion function 1112. The image acquisition unit 111 outputs the image data after the data format conversion to the image processing unit 12 at a bit rate based on the clock signal generated by the crystal oscillator 113); and a server device (fig. 4, external device 30 connected to an external network e.g. a server) that manages data to be used by the conversion circuit or the processor (Paragraph 48, The image acquisition unit 111 reads the optimum circuit information from the circuit information 31-1 to 31-n related to the conversion circuit from the external device 30 based on the determination result of the data format of the image data (S53)).
[Claim 13]
The information processing system according to claim 12, wherein the conversion circuit is a circuit in which logic is rewritable (Paragraph 26, The image acquisition unit 111 configures a logic circuit on the FPGA (FPGAs are field programmable gate arrays that are programmable or rewritable) based on circuit information stored in the nonvolatile memory 112. That is, the image acquisition unit 111 has a data format determination function 1111 based on circuit information 1121 and a data format conversion function 1112 based on circuit information 1122-1 to 1122-n), and the processor rewrites the logic according to a type of the sensor (The image acquisition unit 111 configures a logic circuit on the FPGA (FPGAs are field programmable gate arrays that are programmable or rewritable) based on circuit information and the circuit information will be different for different types of sensors).
[Claim 14]
The information processing system according to claim 13, wherein the server device stores, as the data, management information for managing sensor information compatible with the sensor, and the processor rewrites the logic based on the management information (Paragraphs 42-44, The interface circuit 11 includes an image acquisition unit 111, a nonvolatile memory 115, a crystal oscillator 113, a connector 114, and a connection unit 116. The connection unit 116 is connected to an external network. An external device 30 like a server is connected to the external network. The external device 30 stores circuit information 31-1 to 31-n related to the conversion circuit. The image acquisition unit 111 has a data format determination function based on the circuit information 1151 of the nonvolatile memory 115, and has a data format conversion function based on the circuit information 31-1 to 31-n of the external device 30 and Paragraph 48, The image acquisition unit 111 reads the optimum circuit information from the circuit information 31-1 to 31-n related to the conversion circuit from the external device 30 based on the determination result of the data format of the image data (S53)).
[Claim 15]
The information processing system according to claim 14, wherein the sensor information includes rewrite information for rewriting the logic, the information processing system further comprises a memory that stores the rewrite information, and the processor rewrites the logic based on the rewrite information (Paragraph 26, The image acquisition unit 111 configures a logic circuit on the FPGA based on circuit information stored in the nonvolatile memory 112. That is, the image acquisition unit 111 has a data format determination function 1111 based on circuit information 1121 and a data format conversion function 1112 based on circuit information 1122-1 to 1122-n, as shown in fig. 1).
[Claim 16]
The information processing system according to claim 14, further comprising a memory that stores configuration information regarding the sensor and the conversion circuit, wherein the server device selects the sensor information from the management information based on the configuration information, and the processor rewrites the logic based on the sensor information selected by the server device (Paragraphs 33-35, First, the image acquisition unit 111 reads circuit information 1121 related to the determination circuit from the nonvolatile memory 112 when the power is turned on (S31). The image acquisition unit 111 determines the data format of the imaging apparatus 20 by using the data format determination function 1111 (S32). The image acquisition unit 111 reads the optimum circuit information from the circuit information 1122-1 to 1122-n related to the conversion circuit from the nonvolatile memory 112 based on the determination result of the data format of the image data (S33). Subsequently, the image acquisition unit 111 turns off the power, and then turns on the power again (S34). Thereby, the logic circuit of the image acquisition unit 111 is reconfigured based on the circuit information read in S33. When the logic circuit is reconfigured, the image acquisition unit 111 ends the process. When receiving the image data in this state, the image acquisition unit 111 converts the data format of the image data by the data format conversion function 1112 and outputs it to the image processing unit 12).
[Claim 17]
The information processing system according to claim 14, wherein the sensor information includes driver information regarding a device driver compatible with the sensor, and the processor controls the sensor based on the driver information (Inherently in order to control the sensor by the processor, a driver will need to be used that is compatible with the sensor, otherwise the two devices cannot communicate with each other).
[Claim 18]
The information processing system according to claim 14, wherein the sensor information includes software information regarding signal processing software compatible with the sensor, and the processor processes the image generation data converted by the conversion circuit based on the software information (Paragraphs 25 and 26, The conversion circuit is a circuit for converting the data format of the image data from the imaging device 20 into a uniform data format to be processed by the image processing unit 12. There are a plurality of types of conversion circuits on the assumption that a plurality of imaging devices are connected. The image acquisition unit 111 configures a logic circuit on the FPGA based on circuit information stored in the nonvolatile memory 112. That is, the image acquisition unit 111 has a data format determination function 1111 based on circuit information 1121 and a data format conversion function 1112 based on circuit information 1122-1 to 1122-n).
[Claims 19 and 20]
These are circuit and method claims corresponding to apparatus claim 1 and are therefore analyzed and rejected based upon apparatus claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Eigo et al. (JP Patent # 2011061439A) in view of Yoichi (JP Patent # 201806030A).
[Claim 6]
Eigo fails to teach a sensor board on which the sensor is provided; and a circuit board on which the conversion circuit is provided, wherein the sensor board and the circuit board are formed to be detachably attached, and are formed in such a manner that the sensor and the conversion circuit are electrically connected in a state where the sensor board and the circuit board are attached. However Yoichi teaches a sensor board 22 having a sensor section 222 and a circuit base board 21 on which the connector 211 (interface) is formed (figs. 1 and 4, Paragraph 20) and the first base connector 211 of the base board 21 is detachably engaged with the sensor connector of the sensor board 22. By fitting the first base connector 211 of the base board 21 and the sensor connector of the sensor board 22, the sensor board 22 is mounted and supported on the base board 21 on the front side of the base board 21. Since the first base connector 211 of the base board 21 and the sensor connector of the sensor board 22 have a detachable fitting structure, the sensor board 22 attached to the base board 21 can be replaced, that is, the sensor device set 2 user can remove one sensor board 22 from the base board and replace it with another sensor board 22’ (Paragraph 21).
Therefore taking the combined teachings of Eigo and Yoichi, it would be obvious to one skilled in the art before the effective filing date of the invention to have been motivated to have a sensor board on which the sensor is provided; and a circuit board on which the conversion circuit is provided, wherein the sensor board and the circuit board are formed to be detachably attached, and are formed in such a manner that the sensor and the conversion circuit are electrically connected in a state where the sensor board and the circuit board are attached in order for the sensor board to be easily replaced by a different sensor depending upon the application in which it is used.
[Claim 7]
Yoichi teaches wherein the sensor board and the circuit board are stacked (see fig. 2a, base board 21 and sensor board 22 are stacked) in order to easily replace the sensor board by simply disconnecting the board.
[Claim 8]
Eigo teaches image data and a conversion circuit and an interface different from the interface as taught in claim 1 but fails to teach wherein the sensor board and the circuit board have respective connection connectors and the circuit board has an output connector that is for outputting the data from the conversion circuit. Yoichi teaches a sensor board 22 having a sensor section 222 and a circuit base board 21 on which the connector 211 (interface) is formed (figs. 1 and 4, Paragraph 20) and the first base connector 211 of the base board 21 is detachably engaged with the sensor connector of the sensor board 22 in order to make the data usable for display or other applications.
[Claim 9]
Yoichi teaches wherein the connection connector for each of the sensor board and the circuit board is a coupling connector that couples the sensor board and the circuit board (Paragraph 36, fig. 4, The first base connector 211 is electrically connected to the sensor connector 221 of the sensor board 22, the second base connector is electrically connected to the microcomputer connector 231 of the microcomputer board 23, and the communication connector is electrically connected to the communication connector 241 of the communication board 24) in order to make it easier to connect and disconnect the boards from each other.
[Claim 10]
Eigo teaches image data and a conversion circuit and an interface identical to the interface but fails to teach wherein the sensor board and the circuit board have respective connection connectors and the circuit board has an output connector that is for outputting the data from the conversion circuit. Yoichi teaches a sensor board 22 having a sensor section 222 and a circuit base board 21 on which the connector 211 (interface) is formed (figs. 1 and 4, Paragraph 20) and the first base connector 211 of the base board 21 is detachably engaged with the sensor connector of the sensor board 22 in order to make the data usable for display or other applications.
[Claim 11]
Yoichi teaches wherein the connection connector for each of the sensor board and the circuit board is a coupling connector that couples the sensor board and the circuit board (Paragraph 21, he first base connector 211 of the base board 21 is detachably engaged with the sensor connector of the sensor board 22. By fitting the first base connector 211 of the base board 21 and the sensor connector of the sensor board 22, the sensor board 22 is mounted and supported on the base board 21 on the front side of the base board 21) in order to make it easier to connect and disconnect the boards from each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YOGESH K AGGARWAL whose telephone number is (571)272-7360. The examiner can normally be reached Monday - Friday 9:30-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at 5712727564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOGESH K AGGARWAL/Primary Examiner, Art Unit 2637