DETAILED ACTION
Claims 26-33 are pending. Claims 1-25 and 34-45 are cancelled.
Priority: 6/30/2022
Assignee: Intel
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 26, 29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al.(20140122807).
As per claim 26, Chang discloses:
An apparatus(Chang, [0017 -- system 200 constructed in accordance with the teachings of this disclosure to map data in memory. The example system 200 of FIG. 2 includes a processor 105, a memory controller 120, and a memory module 180 ]) comprising:a cache memory(Chang, [0020 -- The memory controller 120 of the illustrated example includes an example address translator 125, an example memory mapping function cache 130], [0021 -- In the illustrated example, the address translator 125 receives an instruction to access data stored in the memory module 180 at an intermediate address]);
and circuitry coupled to the cache memory(Chang, [0020 -- The example address translator 125 translates an intermediate memory address into a hardware memory address based on a function; The example memory accesser 135 accesses the memory module 180 at the hardware memory address identified by the address translator ], [0033 -- In the illustrated example, the memory access pattern predictor 450 monitors access patterns to a sector of hardware memory. Based on the memory access patterns, the memory access pattern predictor 450 derives and/or selects a memory mapping function to be used in association with one or more intermediate memory sectors storing data corresponding to the sector of hardware memory]), the circuitry to:
perform a selection of a first map function from among multiple map functions(Chang, [0039 -- In the illustrated example, the memory access pattern predictor 450 derives the memory mapping function. However, in some examples, the memory access pattern predictor 450 selects the memory mapping function from a list of known memory mapping functions], [0040 -- The address translator 125 identifies a memory mapping function to be used for translating the intermediate memory address into a hardware memory address]);
generate a mapping of an index to a first set of multiple sets of the cache memory based on the selected first map function(Chang, [0039 -- The memory access pattern predictor 450 stores an association of the derived memory mapping function and the intermediate memory sectors with which it is associated in the memory mapping function cache], [0040 -- The translator 125 applies the identified function to determine the hardware memory address associated with the intermediate memory address (block 730). ]);
and perform a lookup of an entry in the cache memory based at least in part on the mapping(Chang, [0022 -- In the illustrated example, the memory mapping function cache 130 stores associations of intermediate memory sectors (e.g., intermediate memory addresses identified by an intermediate start address and an intermediate end address) and translation functions to be used to translate addresses within the intermediate memory sectors to corresponding hardware addresses within hardware memory sectors (e.g., data stored in the memory module 180)], [0040 -- The memory accesser 135 then accesses (e.g., reads and/or writes) the memory module 180 at the hardware address to complete the memory access operation ]).
As per claim 29, the rejection of claim 26 is incorporated, in addition, Chang discloses:
wherein the first map function is to promote a different access pattern for the cache memory as compared to a second map function of the multiple map functions(Chang, [0039 -- The memory access pattern predictor 450 determines one or more access patterns from an intermediate memory sector to a hardware memory sector (block 610).; in some examples, the memory access pattern predictor 450 selects the memory mapping function from a list of known memory mapping functions]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al.(20140122807), and further in view of Vick et al.(20070283123).
As per claim 27, the rejection of claim 26 is incorporated, in addition, Chang does not explicitly disclose the following, however Vick discloses:
wherein the circuitry is further to select the indicated first map function based at least in part on an indication from a software agent(Vick, [0041 -- In some embodiments, a compiler, operating system, or software diagnostic tool may be configured to determine an appropriate memory virtualization technique based on criteria such as described above. In other embodiments, a user or programmer may direct the computer's operating system and/or compiler to use a particular technique.], [0069 -- As illustrated at 710, this determination may be based on an analysis of predicted virtual memory accesses done at compilation, or may be based on a user policy or received user input, as described above. In some embodiments, the computer system may include a default address translation technique for all applications.], [0072 -- the operating system may be configured to analyze the output of the profiler and to make the necessary changes to reduce translation overhead, as in 750. ]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Vick into the system of Chang for the benefit of efficiently translating the virtual address to the physical address in the computer system, thus providing memory virtualization using a function-based technique, and hence improving overall performance of the system by reducing overhead for accessing a memory of the system and by reducing consumption of large percentage of the processor cycles(Vick, 0039).
As per claim 28, the rejection of claim 27 is incorporated, in addition, Chang does not explicitly disclose the following, however Vick discloses:
wherein the circuitry is further to: determine the indication from the software agent based on a value of a register(Vick, [0041 -- A memory virtualization technique may be selected or determined statically, such as when an application starts or at compilation, in some embodiments. For example, the technique may be determined based on an analysis of predicted memory accesses performed during compilation, or on a policy specified by the programmer.; In some embodiments, a compiler, operating system, or software diagnostic tool may be configured to determine an appropriate memory virtualization technique based on criteria such as described above. In other embodiments, a user or programmer may direct the computer's operating system and/or compiler to use a particular technique.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Vick into the system of Chang for the benefit of efficiently translating the virtual address to the physical address in the computer system, thus providing memory virtualization using a function-based technique, and hence improving overall performance of the system by reducing overhead for accessing a memory of the system and by reducing consumption of large percentage of the processor cycles(Vick, 0039).
Claims 30-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al.(20140122807), and further in view of Zheng et al.(20130097403).
As per claim 30, the rejection of claim 29 is incorporated, in addition, Chang does not explicitly disclose the following, however Zheng discloses:
wherein circuitry is to use a first bit of a relatively low order field of a first address to determine a value of a second bit of a relatively high order second field of a first mapping based on the first map function(Zheng, [0047 -- Address mapping 410 performs a bitwise XOR function 412 between the input memory address 402 column address bits 6-13 and the input memory address 402 row address bits 20-27. The XOR function 412 produces eight output bits as a column address for mapped memory address 404. The eight output bits are placed in bit positions 20-27 of mapped memory address 404.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Zheng into the system of Chang for the benefit of the memory circuit accessing memory cells at memory locations identified by the wear-leveled memory address and the address mapping circuit can increase the efficiency of the wear leveling technique to increase the performance of a memory system and/or to reduce the power consumption of the memory system(Zheng, 0018).
As per claim 31, the rejection of claim 30 is incorporated, in addition, Chang does not explicitly disclose the following, however Zheng discloses:
wherein, based on the first map function, the circuitry is to include the first bit as the second bit of the relatively high order second field(Zheng, [0029 -- In an alternative embodiment additionally employing a fixed shift, a fixed shift operation treats a group of bits as a group and arithmetically shifts the group by a constant amount. For example, a fixed shift operation may add 30 to a column address portion of a memory address.], [0036 -- In one embodiment, the input memory address column address bits and a lower-bit-position group of the input memory address row address bits are reassigned to be the mapped memory address row address bits.], [0041 -- The address mapping circuit then performs an arithmetic function (e.g., addition or subtraction) on the pseudorandom offset and the column address COL in the input memory address to generate a shifted column address], [0048 -- Block rotation (not to be confused with the block bits) uses a scheme to periodically shift blocks of memory locations to different locations in physical memory]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Zheng into the system of Chang for the benefit of the memory circuit accessing memory cells at memory locations identified by the wear-leveled memory address and the address mapping circuit can increase the efficiency of the wear leveling technique to increase the performance of a memory system and/or to reduce the power consumption of the memory system(Zheng, 0018).
As per claim 32, the rejection of claim 30 is incorporated, in addition, Chang does not explicitly disclose the following, however Zheng discloses:
wherein, based on the first map function, the circuitry is to perform an XOR of the first bit with one or more other bits of the first address to determine the value of the second bit(Zheng, [0047 -- Address mapping 410 performs a combination of reassignment and XOR remapping on input memory address 402.; Address mapping 410 performs a bitwise XOR function 412 between the input memory address 402 column address bits 6-13 and the input memory address 402 row address bits 20-27. The XOR function 412 produces eight output bits as a column address for mapped memory address 404. The eight output bits are placed in bit positions 20-27 of mapped memory address 404.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Zheng into the system of Chang for the benefit of the memory circuit accessing memory cells at memory locations identified by the wear-leveled memory address and the address mapping circuit can increase the efficiency of the wear leveling technique to increase the performance of a memory system and/or to reduce the power consumption of the memory system(Zheng, 0018).
As per claim 33, the rejection of claim 29 is incorporated, in addition, Chang does not explicitly disclose the following, however Zheng discloses:
wherein the circuitry is to use a first bit of a relatively high order field of a first address to determine a value of a second bit of a relatively low order second field of a first mapping according to the first map function(Zheng, [0048 -- Wear leveling 420 performs a combination of block rotation and a positional shift on mapped memory address; Block rotation (not to be confused with the block bits) uses a scheme to periodically shift blocks of memory locations to different locations in physical memory.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Zheng into the system of Chang for the benefit of the memory circuit accessing memory cells at memory locations identified by the wear-leveled memory address and the address mapping circuit can increase the efficiency of the wear leveling technique to increase the performance of a memory system and/or to reduce the power consumption of the memory system(Zheng, 0018).
Response to Arguments
Applicant's arguments filed 3/31/2026 have been fully considered.
Regarding the rejections under 35 USC 112(b) of claims 30 and 32 in the previous OA mailed 3/5/2026, based on the applicant’s amendments, these rejections on the prior basis have been dropped.
Additionally, the applicant is contending the following rejections are improper and should be dropped(Remarks, p. 4):
Claims 26 and 29 are rejected under 35 U.S.C. §102(a)(l) as allegedly being unpatentable over Chang et al., US Pub No. 2014/0122807 (hereinafter “Chang”).
Claims 27-28 are rejected under 35 U.S.C. §103 as allegedly being unpatentable over Chang, and further in view of Vick et al., US Pub No. 2007/0283123 (hereinafter “Vick”).
Claims 30-33 are rejected under 35 U.S.C. §103 as allegedly being unpatentable over Chang, and further in view of Zheng et al., US Pub No. 2013/0097403 (hereinafter “Zheng”).
The USPTO disagrees with the applicant’s contention for the following reasons.
Firstly, regarding newly amended claim 26:
An apparatus comprising:a cache memory; andcircuitry coupled to the cache memory, the circuitry to:
perform a selection of a first map function from among multiple map functions;
generate a mapping of an index to a first set of multiple sets of the cache memory based on the selected first map function; and
perform a lookup of an entry in the cache memory based at least in part on the mapping.
It is the position of the USPTO that the prior art of Chang does disclose these limitations.
For instance, regarding one limitation:
perform a selection of a first map function from among multiple map functions;
The prior art of Chang discloses this limitation in at-least [0040]. Please see the rejection above for further clarification.
Regarding a second limitation:
generate a mapping of an index to a first set of multiple sets of the cache memory based on the selection;
The evidence of support for this particular limitation is in Fig. 2B, [0055] and [0087]. The “generating” occurs when the mapping function is implemented.
The prior art of Chang discloses this limitation in [0040] as clarified in the rejection above.
Regarding a third limitation of the claim:
perform a lookup of an entry in the cache memory based at least in part on the mapping;
This limitation is supported in the Spec, Fig. 1B, [0046], [0049], and 0087 among others. The prior art of Chang discloses this limitation in at-least [0022] and [0040] as clarified in the rejection above.
All amended claims have been addressed. All the prior art rejections have been elaborated, modified, and ultimately maintained.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bernat et al.(20160321187) where data and a memory address associated with the data may be received. A hash value of the memory address may be calculated by using a first hash function. The data may be stored at a cache set of a plurality of cache sets of a cache memory based on the hash value calculated from the first hash function. A determination may be made as to whether the storing of the data at the cache set of the plurality of cache sets of the cache memory is associated with a conflict ratio of the cache memory exceeding a threshold ratio. In response to the conflict ratio exceeding the threshold ratio, a second hash value of a second memory address associated with a second data may be calculated by using a second hash function that is different than the first hash function(Bernat, abstract).
Harris et al.(2018/0307617) involves executing a series of program instructions specifying a set of data accesses to a memory accessible to multi-processors through a set of memory channels. A respective specified location to a respective translated location within the memory is permuted during executing for some of the set of data accesses. The respective translated location is accessed within the memory instead of the respective specified location during the executing, where the specified location is accessible through one of the memory channels and the translated location is accessible through a different one of the memory channels(Harris, abstract).
Kozhikkottu et al.(20200310979) where the apparatus has a page table circuit that receives a virtual address and generates a portion of a physical address. A mapping rule table is coupled to the page table circuit. The mapping rule table receives mapping metadata of a page of a system memory and outputs a mapping rule for the page based on the mapping metadata. The kernel writes the mapping metadata of the page based on memory access characteristics of an application to which the page is allocated. The permutation circuit permutes a subset of a page offset portion of the physical address based on the mapping rule. The memory controller receives the physical address comprising the permuted subset of the page offset portion of the physical address and sends physical address to the system memory to enable access to the page(Kozhikkottu, abstract).
Ware et al.(5390308) where the method for remapping of row addresses of memory requests to random access memory involves using a master device such as a central processing unit (CPU) which issues a memory request comprising a memory address to the memory. The memory consists of multiple memory banks, each bank having a number of rows of memory elements. Associated with each memory bank is a sense amplifier latch which functions as a row cache to the memory bank. The memory address issued as part of the memory request is composed of device identification bits to identify the memory bank to access, row bits which identify the row to access, and column address bits which identify the memory element within the row to access(Ware, abstract).
Morgan et al.(20200159674) where the method involves selecting a mapping function from a set of mapping functions that are supported by a memory device in which each mapping function in the set maps logical addresses received at the memory device to physical addresses within a memory array of the memory device. An access command comprising a logical address of data stored in the memory array is received. A physical address within the memory array is determined based on the logical address and the selected mapping function. The data stored in the memory array is accessed based on the physical address(Morgan, abstract).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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