DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 22, 2024 has been considered by the examiner. An initialed copy of the IDS is included with this Office Action.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. The following features must be shown or the feature(s) cancelled from the claims:
the “input of the combiner is coupled to an output of the mixer” in claim 5, line 2. The recited combiner is “configured to combine predistortion signal in the predistortion signal path with a main signal in the main signal path” (see claim 1, lines 5-7) thereby corresponding to “combiner stage 506” in FIGs. 6A and 6C, respectively. However, neither FIG. 6A nor FIG. 6C shows the input of “combiner stage 506” as being coupled to an output of a mixer (see “mixer stage 412”).
“upconverting the filtered version of the analog main signal,” “upconverting the filtered version of the analog predistortion signal,” and “combining the upconverted version of the analog main signal with the upconverted version of the analog predistortion signal” in claim 15, lines 6-12. FIG. 6A and FIG. 6C, respectively, shows that the filtered signals are combined (via “combiner stage 506”) and then the combined signal is upconverted (via “mixer stage 412”) but the figures do not show upconverting each signal and then combining the respective upconverted signals as recited.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
The claims are objected to because of the following informalities:
in claim 1, line 1, the comma should be deleted;
in claim 13, line 1, the comma should be deleted; and
in claim 20, line 1, the comma should be deleted.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 7 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regard to claims 6 and 16, “DAC type” on line 1 of the respective claims renders the respective claims indefinite because it is unclear what “type” is intended to convey. (See MPEP 2173.05(b).III.E) For example, it is unclear what features or commonalities are shared by the first DAC and the second DAC such that they are the “same DAC type” within the scope of the invention.
Dependent claim(s) are rejected under the same ground(s) as the claim(s) from which it depends.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 12-15 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McLaurin (US Patent No. 8,824,980 B2).
With regard to claim 1, Figures 1 and 2 of McLaurin disclose the claimed invention including an apparatus comprising:
a main signal path comprising a first digital-to-analog converter (52), a power amplifier (80) and a combiner (75) disposed in the main signal path between an output of the first DAC and an input of the power amplifier; and
a predistortion signal path comprising a second digital-to-analog converter (62) wherein the combiner is configured to combine a predistortion signal with a main signal in the main signal path.
With regard to claim 2, Figure 2 of McLaurin discloses the claimed invention including the main signal path comprising a transmit chain (85) coupled between the output of the first DAC (52) and the input of the power amplifier (80) and wherein the combiner (75) is disposed in the main signal path between the output of the first DAC (52) and the transmit chain (85).
With regard to claim 3, Figure 1 of McLaurin discloses the claimed invention including the main signal path comprising a transmit chain (e.g. 54 and 56) between the output of the first DAC (52) and the input of the power amplifier (80) wherein the combiner is disposed in the transmit chain.
With regard to claim 4, Figure 2 of McLaurin discloses the claimed invention including the transmit chain comprising a filter (54) wherein an input of the combiner (75) is coupled to an output of the filter (54).
With regard to claim 5, Figure 1 of McLaurin discloses the claimed invention including the transmit chain comprising a mixer (56) wherein an input of the combiner (75) is coupled to an output of the mixer.
With regard to claim 12, Figures 1 and 2 of McLaurin disclose the claimed invention including the predistortion signal path further comprises digital predistortion (DPD) logic (95 and 20) wherein the DPD logic is configured to adjust for nonlinearity of the power amplifier (see column 1, lines 24-29) and the output of the DPD logic is coupled to an input of the second DAC (62).
With regard to claim 13, Figures 1 and 2 of McLaurin disclose the claimed invention including a method comprising:
converting a digital main signal into an analog main signal, via a first digital-to-analog converter (52) in a main path signal;
converting a digital predistortion signal into an analog predistortion signal, via a second digital-to-analog converter (62) in a predistortion path signal;
combining, via a combiner (75) disposed in the main signal path, a processed version of the analog main signal (output of 56 in Figure 1; or output of 54 in Figure 2) with a processed version of the analog predistortion signal (output of 66 in Figure 1; or output of 64 in Figure 2), to create an analog combined signal; and
amplifying, via a power amplifier (80) disposed in the main signal path, the analog combined signal.
With regard to claim 14, Figure 2 of McLaurin discloses the claimed invention including filtering the analog main signal (54) to generate a filtered version of the analog main signal; and filtering the analog predistortion signal (64) to generate a filtered version of the analog predistortion signal, wherein combining (via 75) comprises combining the filtered version of the analog main signal with the filtered version of the analog predistortion signal to create the combined analog signal.
With regard to claim 15, Figure 1 of McLaurin discloses the claimed invention including filtering the analog main signal (via 54) to generate a filtered version of the analog main signal; filtering the analog predistortion signal (via 64) to generate a filtered version of the analog predistortion signal; upconverting the filtered version of the analog main signal (via 56 and 70); and upconverting the filtered version of the analog predistortion signal (via 66 and 70) wherein the combining (via 75) comprises combining the upconverted version of the analog main signal with the upconverted version of the analog predistortion signal to create the analog combined signal.
With regard to claim 19, Figures 1 and 2 of McLaurin disclose the claimed invention including applying digital predistortion, with digital predistortion (DPD) logic (95 and 20) in the predistortion signal main, to the digital main signal (Tx Data) wherein the DPD logic is configured to adjust for nonlinearity of the power amplifier (see column 1, lines 24-29) and the output of the DPD logic is coupled to an input of the second DAC (62).
With regard to claim 20, Figures 1 and 2 of McLaurin disclose the claimed invention including an apparatus comprising:
first means for converting (52) a digital main signal into an analog main signal, the first means for converting being disposed in a main path signal;
second means for converting (62) a digital predistortion signal into an analog predistortion signal, second means for converting being disposed in a predistortion path signal;
means for combining (75) a processed version of the analog main signal (output of 180 in Figure 1; or output of 54 in Figure 2) with a processed version of the analog predistortion signal (output of 66 in Figure 1; or output of 64 in Figure 2), to create an analog combined signal, the means for combining being disposed in the main signal path; and
means for amplifying (80) the analog combined signal, the means for amplifying being disposed in the main signal path.
Claims 1-3, 10, 13, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rexberg et al. (US Patent No. 7,505,530 B2).
With regard to claim 1, Figure 8 of Rexberg et al. discloses the claimed invention including an apparatus comprising:
a main signal path (A-branch) comprising a first digital-to-analog converter (D/A), a power amplifier (element after combiner) and a combiner disposed in the main signal path between an output of the first DAC and an input of the power amplifier; and
a predistortion signal path (B-branch) comprising a second digital-to-analog converter (D/A) wherein the combiner is configured to combine a predistortion signal with a main signal in the main signal path.
(See column 3, lines 20-28 and column 4, line 61 - column 5, line 5.)
With regard to claim 2, Figure 8 of Rexberg et al. discloses the claimed invention including the main signal path comprising a transmit chain (e.g. “Attn”) coupled between the output of the first DAC and the input of the power amplifier and wherein the combiner is disposed in the main signal path between the output of the first DAC and the transmit chain (“Attn”).
With regard to claim 3, Figure 8 of Rexberg et al. discloses the claimed invention including the main signal path comprising a transmit chain (e.g. “Attn” and the combiner) between the output of the first DAC and the input of the power amplifier wherein the combiner is disposed in the transmit chain.
With regard to claim 10, Rexberg et al. discloses the claimed invention including the second DAC is configured to have a higher sampling rate than the first DAC or the second DAC is configured to have a lower resolution than the first DAC. (See abstract; column 3, lines 22-27; and column 4, line 63 – column 5, line 1.)
With regard to claim 13, Figure 8 of Rexberg et al. discloses the claimed invention including a method comprising:
converting a digital main signal into an analog main signal, via a first digital-to-analog converter (D/A) in a main path signal (A-branch);
converting a digital predistortion signal into an analog predistortion signal, via a second digital-to-analog converter (D/A) in a predistortion path signal (B-branch);
combining, via a combiner disposed in the main signal path the analog main signal with a processed version of the analog predistortion signal (output of “Attn”), to create an analog combined signal; and
amplifying, via a power amplifier disposed in the main signal path, the analog combined signal.
With regard to claim 18, Rexberg et al. discloses the claimed invention including the second DAC is configured to have a higher sampling rate than the first DAC or the second DAC is configured to have a lower resolution than the first DAC. (See abstract; column 3, lines 22-27; and column 4, line 63 – column 5, line 1)
With regard to claim 20, Figure 8 of Rexberg et al. discloses the claimed invention including:
first means for converting a digital main signal into an analog main signal, the first means for converting (D/A) being disposed in a main path signal (A-branch);
second means for converting a digital predistortion signal into an analog predistortion signal, the second means for converting (D/A) being disposed in a predistortion path signal (B-branch);
means for combining the analog main signal with a processed version of the analog predistortion signal (output of “Attn”), to create an analog combined signal, the means for combining being disposed in the main signal path (A-branch); and
means for amplifying the analog combined signal, the means for amplifying being disposed in the main signal path (A-branch).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over McLaurin.
With regard to claim 6, McLaurin discloses the claimed invention except for the first DAC being the same DAC-type as the second DAC. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the same type of DAC for the first DAC and second DAC based on the availability of the types of DACs. Furthermore, using the same type of DACs for the main signal path and the predistortion signal path ensures identical conversion quality in both paths.
With regard to claim 11, McLaurin discloses the claimed invention except for the second DAC being configured to use a lower full-scale current than the first DAC. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a lower full-scale current for the “second DAC” in the predistortion path than for the “first DAC” in the main signal path in order to reduce power consumption.
With regard to claim 16, McLaurin discloses the claimed invention except for the first DAC being a different DAC-type than the second DAC. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the same type of DAC for the first DAC and second DAC based on the availability of the types of DACs. Furthermore, using a different DAC-type in the main signal path and the predistortion signal path allows greater flexibility for adapting to requirements/considerations such as speed or power consumption.
Claims 6, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Rexberg et al.
With regard to claim 6, Rexberg et al. discloses the claimed invention except for the first DAC being the same DAC-type as the second DAC. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the same type of DAC for the first DAC and second DAC based on the availability of the types of DACs. Furthermore, using the same type of DACs for the main signal path and the predistortion signal path ensures identical conversion quality in both paths.
With regard to claim 11, Rexberg et al. discloses the claimed invention except for the second DAC being configured to use a lower full-scale current than the first DAC. Since the predistortion signal has a lower amplitude than the main signal (see Fig. 2), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a lower full-scale current for the “second DAC” in the predistortion path than for the “first DAC” in the main signal path in order to reduce power consumption.
With regard to claim 16, Rexberg et al. discloses the claimed invention except for the first DAC being a different DAC-type than the second DAC. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the same type of DAC for the first DAC and second DAC based on the availability of the types of DACs. Furthermore, using a different DAC-type in the main signal path and the predistortion signal path allows greater flexibility for adapting to requirements/considerations such as speed or power consumption.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over McLaurin or Rexberg et al. as applied to claim 6, respectively, above, and further in view of Schafferer (US Patent No. 10,230,387 B2). McLaurin or Rexberg et al. discloses the claimed invention except for the first DAC and the second DAC comprising current-steering DACS. Schafferer discloses using current steering DACs to generate analog RF signals from digital RF signals. (See column 1, lines 36-41) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the common/popular current steering DACs in the circuit of McLaurin or Rexberg et al. since current-steering DACs provide high accuracy while maintaining relatively low power consumption.
Claims 8, 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Rexberg et al. as applied to claims 1 and 13, respectively, above, and further in view of Wloczysiak (US Patent No. 9,258,156 B2 cited in the IDS submitted November 22, 2024).
With regard to claims 8 and 17, Rexberg et al. discloses the claimed invention except for the second DAC having a wider bandwidth than the first DAC. Wloczysiak teaches that a DAC in a predistortion path (i.e. the “second DAC”) must be configured to expanded bandwidth requirements compared to the DAC in a main signal (i.e. the “first DAC”) in order to successfully operate on the signals generated by the DPD in the predistortion path. (See column 6, line 58 – column 7, line 1) Since Rexberg et al. discloses the bandwidth of the predistortion signal being wider than the bandwidth of the main signal (see Fig. 2 and column 2, lines 55-60), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use second DAC in the predistortion path (B-branch) of Rexberg et al. that has a wider bandwidth than the first DAC in order to successfully operate on the predistortion signals to compensate for the non-linearity of the power amplifier.
With regard to claim 9, Rexberg et al. in view of Wloczysiak discloses the claimed invention including the bandwidth of the second DAC being 3-5 times wider than the bandwidth of the first DAC. (See Rexberg et al., Fig. 2 and column 2, lines 55-60 and Wloczysiak, column 5, lines 51-53)
Conclusion
Please note that non-cited portions of the references may also read on the claim limitations. Therefore, the references should be considered in their entirety.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references disclose digital predistortion systems that read on the claimed inventions: Oishi et al. (US Patent No. 6,567,478 B2); Braithwaite (US Patent No. 7,095,799 B2); Ocenasek et al. (US Patent No. 7,321,635 B2); and Kim et al. (US Patent No. 8,548,403 B2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Betsy Deppe whose telephone number is 571-272-3054. The examiner can normally be reached Monday, Wednesday and Thursday, 7:00 am - 3:00 pm (ET).
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/BETSY DEPPE/Primary Examiner, Art Unit 2633