DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed June 23, 2026 has been entered. Claims 1-20 are pending.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Objections
Claim 4 is objected to because of the following informalities: “the other filter” on line 2 should be “the another filter”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 4 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification, at the time the application was filed, does not describe an apparatus with the two filters (see “the transmit chain comprises another filter” in claim 4, lines 1-2 and the “filter coupled between an output of the combiner and the input of the power amplifier” in claim 1, lines 4-5). Claim 1 corresponds to the embodiment shown in FIG. 6A. Neither FIG. 6A nor the corresponding description of FIG. 6A includes “another filter” as recited in claim 4 in combination with the “filter” recited in claim 1. Therefore, claim 4 fails to comply with the written description requirement.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Braithwaite (US Patent No. 7,095,799 B2 cited in the Office Action of March 25, 2026).
Regarding claim 1, FIG. 3 of Braithwaite disclose the claimed invention including an apparatus comprising:
a main signal path (203) comprising a “first” digital-to-analog converter (222), a power amplifier (242), a filter (240), and a combiner (219) disposed in the main signal path between an output of the first DAC and an input of the power amplifier wherein the filter is coupled between an output of the combiner and the input of the power amplifier; and
a predistortion signal path (205) comprising a “second” digital-to-analog converter (218) wherein the combiner (219) is configured to combine a predistortion signal with a main signal in the main signal path.
Regarding claim 2, FIG. 3 of Braithwaite discloses the claimed invention including the main signal path (203) comprising a transmit chain (e.g. 236 and 240) coupled between the output of the “first” DAC (222) and the input of the power amplifier (242) and wherein the combiner (219) is disposed in the main signal path between the output of the “first” DAC (222) and the transmit chain (238).
Regarding claim 3, FIG. 3 of Braithwaite discloses the claimed invention including the main signal path (203) comprising a transmit chain (e.g. 219, 236 and 240) between the output of the “first” DAC (222) and the input of the power amplifier (242) wherein the combiner (219) is disposed in the transmit chain.
Regarding claim 4, FIG. 3 of Braithwaite discloses the claimed invention including the transmit chain comprising another filter (234) wherein an input of the combiner (75) is coupled to an output of the another filter (234).
Regarding claim 12, FIG. 3 of Braithwaite discloses the claimed invention including the predistortion signal path (205) further comprising digital predistortion (DPD) logic (212) wherein the DPD logic (212) is configured to adjust for nonlinearity of the power amplifier (see column 6, lines 36-42) and the output of the DPD logic is coupled to an input of the “second” DAC (218).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over McLaurin (US Patent No. 8,824,980 B2 cited in the Office Action of March 25, 2025) in view of Braithwaite.
Regarding claim 1, Figure 2 of McLaurin disclose the claimed invention including an apparatus comprising:
a main signal path comprising a first digital-to-analog converter (52), a power amplifier (80) and a combiner (75) disposed in the main signal path between an output of the first DAC and an input of the power amplifier; and
a predistortion signal path comprising a second digital-to-analog converter (62) wherein the combiner is configured to combine a predistortion signal with a main signal in the main signal path.
However, McLaurin does not disclose a filter coupled between an output of the combiner and the input of the power amplifier. FIG. 3 of Braithwaite discloses a filter (240) coupled between an output of a combiner (219) and the input of the power amplifier (242). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a filter coupled between the output of combiner 75 and power amplifier 80 in McLaurin in order to limit the bandwidth of the signal to the assigned channel for transmission. (See Braithwaite, column 7, line 66 – column 8, line 6)
Regarding claim 2, McLaurin in view of Braithwaite disclose the claimed invention including the main signal path comprising a transmit chain (85 in Figure 2 of McLaurin) coupled between the output of the first DAC (52 in Figure 2 of McLaurin) and the input of the power amplifier (80 in Figure 2 of McLaurin) and wherein the combiner (75 in Figure 2 of McLaurin) is disposed in the main signal path between the output of the first DAC (52 in Figure 2 of McLaurin) and the transmit chain (85 in Figure 2 of McLaurin).
Regarding claim 3, McLaurin in view of Braithwaite disclose the claimed invention including the main signal path comprising a transmit chain (e.g. 54, 75 and 85 in Figure 2 of McLaurin) between the output of the first DAC (52 in Figure 2 of McLaurin) and the input of the power amplifier (80 in Figure 2 of McLaurin) wherein the combiner is disposed in the transmit chain.
Regarding claim 4, McLaurin in view of Braithwaite disclose the claimed invention including the transmit chain comprising another filter (54 in Figure 2 of McLaurin) wherein an input of the combiner (75 in Figure 2 of McLaurin) is coupled to an output of the another filter (54 in Figure 2 of McLaurin).
Regarding claim 12, McLaurin in view of Braithwaite disclose the claimed invention including the predistortion signal path further comprises digital predistortion (DPD) logic (95 and 20 in Figure 2 of McLaurin) wherein the DPD logic is configured to adjust for nonlinearity of the power amplifier (see McLaurin, column 1, lines 24-29) and the output of the DPD logic is coupled to an input of the second DAC (62 in Figure 2 of McLaurin).
Claims 1-3, 10, 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Rexberg et al. (US Patent No. 7,505,530 B2 cited in the Office Action of March 25, 2026) in view of Asuri et al. (US Patent No. 9,397,711 B2) and Braithwaite.
Regarding claim 1, Fig. 8 of Rexberg et al. discloses the claimed invention including an apparatus comprising:
a main signal path (A-branch) comprising a first digital-to-analog converter (D/A), a power amplifier (element after combiner) and a combiner disposed in the main signal path between an output of the first DAC and an input of the power amplifier; and
a predistortion signal path (B-branch) comprising a second digital-to-analog converter (D/A) wherein the combiner is configured to combine a predistortion signal with a main signal in the main signal path.
(See column 3, lines 20-28 and column 4, line 61 - column 5, line 5)
However, Rexberg et al. does not disclose a filter coupled between the output of the combiner and the input of the power amplifier. FIG. 4 of Asuri et al. discloses a predistortion transmitter that filters (via 322) a predistorted signal wherein the filtered signal is subsequently amplified via a power amplifier (326 and 340). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to filter the analog combined signal in Rexberg et al. in order to limit the bandwidth of the signal to the assigned channel for transmission. (See Braithwaite, column 7, line 66 – column 8, line 6)
Regarding claim 2, Rexberg et al. in view of Asuri et al. and Braithwaite disclose the claimed invention including Figure 8 of Rexberg et al. discloses the claimed invention including the main signal path comprising a transmit chain (“Attn” in Fig. 8 of Rexberg et al.) coupled between the output of the first DAC and the input of the power amplifier and wherein the combiner is disposed in the main signal path between the output of the first DAC and the transmit chain (“Attn”).
Regarding claim 3, Rexberg et al. in view of Asuri et al. and Braithwaite disclose the claimed invention including the main signal path comprising a transmit chain (“Attn” and the combiner in Fig. 8 of Rexberg et al.) between the output of the first DAC and the input of the power amplifier wherein the combiner is disposed in the transmit chain.
Regarding claim 10, Rexberg et al. in view of Asuri et al. and Braithwaite disclose the claimed invention including the second DAC being configured to have a higher sampling rate than the first DAC or the second DAC being configured to have a lower resolution than the first DAC. (See Rexberg et al., abstract; column 3, lines 22-27; and column 4, line 63 – column 5, line 1)
Regarding claim 13, Figure 8 of Rexberg et al. discloses the claimed invention including a method comprising:
converting a digital main signal into an analog main signal, via a first digital-to-analog converter (D/A) in a main path signal (A-branch);
converting a digital predistortion signal into an analog predistortion signal, via a second digital-to-analog converter (D/A) in a predistortion path signal (B-branch);
combining, via a combiner disposed in the main signal path the analog main signal with a processed version of the analog predistortion signal (output of “Attn”), to create an analog combined signal; and
amplifying, via a power amplifier disposed in the main signal path, the analog combined signal.
However, Rexberg et al. does not disclose filtering the analog combined signal to generate a filtered version of the analog combined signal wherein the filtered version of the analog combined signal is amplified to create an amplified analog combined signal. FIG. 4 of Asuri et al. discloses a predistortion transmitter that filters (via 322) a predistorted signal wherein the filtered signal is subsequently amplified via a power amplifier (326 and 340). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to filter the analog combined signal in Rexberg et al. in order to limit the bandwidth of the signal to the assigned channel for transmission. (See Braithwaite, column 7, line 66 – column 8, line 6)
Regarding claim 18, Rexberg et al. in view of Asuri and Braithwaite discloses the claimed invention including the second DAC is configured to have a higher sampling rate than the first DAC or the second DAC is configured to have a lower resolution than the first DAC. (See Rexberg et al., abstract; column 3, lines 22-27; and column 4, line 63 – column 5, line 1)
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Braithwaite as applied to claim 3 above, and further in view of Asuri et al. Braithwaite discloses the claimed invention including the transmit chain comprising a mixer (236). However, Braithwaite does not disclose the mixer as between the output of the filter and input of the power amplifier. FIG. 4 of Asuri et al. discloses a transmitter with predistortion that comprises a mixer (324) between the output of a filter (322) and the input of a “power amplifier“ (wherein 326 and 340 form a “power amplifier”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to reverse the order of the mixer 236 and filter 240 in Braithwaite so that the mixer is between the filter and the power amplifier since reversing or rearranging the order of a mixer and a filter is an obvious modification that does not affect the functionality of the components themselves. (See also MPEP 2144.04(VI))
Claim 5 is also rejected under 35 U.S.C. 103 as being unpatentable over McLaurin in view of Braithwaite as applied to claim 3 above, and further in view of Asuri et al. McLaurin in view of Braithwaite discloses the claimed invention including the transmit chain comprising a mixer (236). However, McLaurin in view of Braithwaite does not disclose the mixer as between the output of the filter and input of the power amplifier. FIG. 4 of Asuri et al. discloses a transmitter with predistortion that comprises a mixer (324) between the output of a filter (322) and the input of a “power amplifier“ (wherein 326 and 340 form a “power amplifier”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to reverse the order of the mixer and filter in McLaurin in view of Braithwaite so that the mixer is between the filter and the power amplifier since reversing or rearranging the order of a mixer and a filter is an obvious modification that does not affect the functionality of the components themselves. (See also MPEP 2144.04(VI))
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over a. Braithwaite; b. McLaurin in view of Braithwaite; or c. Rexberg et al. in view of Asuri et al. and Braithwaite as applied to claim 1 in the rejections above.
Regarding claim 6, a. Braithwaite; b. McLaurin in view of Braithwaite; or c. Rexberg et al. in view of Asuri et al. and Braithwaite disclose the claimed invention except for the first DAC being the same DAC architecture as the second DAC. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the same DAC architecture for the first DAC and second DAC based on the availability of the DACs. Furthermore, using the same DAC architecture for the main signal path and the predistortion signal path ensures identical conversion quality in both paths.
Regarding claim 11, a. Braithwaite; b. McLaurin in view of Braithwaite; or c. Rexberg et al. in view of Asuri et al. and Braithwaite disclose the claimed invention except for the second DAC being configured to use a lower full-scale current than the first DAC. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a lower full-scale current for the “second DAC” in the predistortion path than for the “first DAC” in the main signal path in order to reduce power consumption.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over each combination of reference(s) as applied to claim 6 above, and further in view of Schafferer (US Patent No. 10,230,387 B2 cited in the Office Action of March 25, 2026). Each combination of reference(s) disclose the claimed invention except for the first DAC and the second DAC comprising current-steering DACS. Schafferer discloses using current steering DACs to generate analog RF signals from digital RF signals. (See column 1, lines 36-41) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the common/popular current steering DACs in the circuit of the respective combination of references since current-steering DACs provide high accuracy while maintaining relatively low power consumption.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Rexberg et al. in view of Braithwaite as applied to claim 1 above, and further in view of Wloczysiak (US Patent No. 9,258,156 B2 cited in the IDS submitted November 22, 2024).
Regarding claim 8, Rexberg et al. in view of Braithwaite disclose the claimed invention except for the second DAC having a wider bandwidth than the first DAC. Wloczysiak teaches that a DAC in a predistortion path (i.e. the “second DAC”) must be configured to expanded bandwidth requirements compared to the DAC in a main signal (i.e. the “first DAC”) in order to successfully operate on the signals generated by the DPD in the predistortion path. (See column 6, line 58 – column 7, line 1) Since Rexberg et al. in view of Braithwaite disclose that the bandwidth of the predistortion signal is wider than the bandwidth of the main signal (see Rexberg et al., Fig. 2 and column 2, lines 55-60), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use second DAC in the predistortion path (B-branch) of Rexberg et al. in view of Braithwaite that has a wider bandwidth than the first DAC in order to successfully operate on the predistortion signals to compensate for the non-linearity of the power amplifier.
Regarding claim 9, Rexberg et al. in view of Braithwaite and Wloczysiak disclose the claimed invention including the bandwidth of the second DAC being 3-5 times wider than the bandwidth of the first DAC. (See Rexberg et al., Fig. 2 and column 2, lines 55-60 and Wloczysiak, column 5, lines 51-53)
Claims 13-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over McLaurin (US Patent No. 8,824,980 B2 cited in the Office Action of March 25, 2025) in view of Braithwaite in view of Asuri et al.
Regarding claim 13, Figure 2 of McLaurin disclose the claimed invention including a method comprising:
converting a digital main signal into an analog main signal, via a first digital-to-analog converter (52) in a main path signal;
converting a digital predistortion signal into an analog predistortion signal, via a second digital-to-analog converter (62) in a predistortion path signal;
combining, via a combiner (75) disposed in the main signal path, a processed version of the analog main signal (output of 56 in Figure 1; or output of 54 in Figure 2) with a processed version of the analog predistortion signal (output of 66 in Figure 1; or output of 64 in Figure 2), to create an analog combined signal; and
amplifying, via a power amplifier (80) disposed in the main signal path, the analog combined signal.
However, McLaurin does not disclose filtering the analog combined signal to generate a filtered version of the analog combined signal wherein the filtered version of the analog combined signal is amplified to create an amplified analog combined signal. FIG. 3 of Braithwaite discloses filtering (240) a modulated signal wherein the filtered signal is amplified via a power amplifier (242). Furthermore, FIG. 4 of Asuri et al. discloses a predistortion transmitter that filters (via 322) a signal prior to mixing/modulating (via 324) the signal for input to a power amplifier (326 and 340). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a filter to filter the analog combined signal in McLaurin prior to modulator 85 in order to limit the bandwidth of the signal to the assigned channel for transmission. (See Braithwaite, column 7, line 66 – column 8, line 6) Reversing or rearranging the order of a mixer and a filter is an obvious modification that does not affect the functionality of the components themselves. (See also MPEP 2144.04(VI))
Regarding claim 14, McLaurin in view of Braithwaite and Asuri et al. disclose the claimed invention including filtering the analog main signal (54 in Figure 2 of McLaurin) to generate a filtered version of the analog main signal; and filtering the analog predistortion signal (64 in Figure 2 of McLaurin) to generate a filtered version of the analog predistortion signal, wherein combining (via 75 in Figure 2 of McLaurin) comprises combining the filtered version of the analog main signal with the filtered version of the analog predistortion signal to create the combined analog signal.
Regarding claim 15, McLaurin in view of Braithwaite and Asuri et al. disclose the claimed invention including upconverting the filtered version of the analog combined signal wherein amplifying the filtered version of the analog combined signal comprises amplifying the upconverted version of the analog combined signal. (See 85 in Figure 2 of McLaurin and 324 in FIG. 4 of Asuri et al.)
Regarding claim 16, McLaurin in view of Braithwaite and Asuri et al. discloses the claimed invention except for the first DAC being the same DAC architecture as the second DAC. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the same DAC architecture for the first DAC and second DAC based on the availability of the DACs. Furthermore, using the same DAC architecture for the main signal path and the predistortion signal path ensures identical conversion quality in both paths
Regarding claim 19, McLaurin in view of Braithwaite and Asuri et al. disclose the claimed invention including applying digital predistortion, with digital predistortion (DPD) logic (95 and 20 in Figure 2 of McLaurin) in the predistortion signal main, to the digital main signal (Tx Data) wherein the DPD logic is configured to adjust for nonlinearity of the power amplifier (see McLaurin, column 1, lines 24-29) and the output of the DPD logic is coupled to an input of the second DAC (62 in Figure 2 of McLaurin)
Regarding claim 20, Figure 2 of McLaurin disclose the claimed invention including an apparatus comprising:
first means for converting (52) a digital main signal into an analog main signal, the first means for converting being disposed in a main path signal;
second means for converting (62) a digital predistortion signal into an analog predistortion signal, second means for converting being disposed in a predistortion path signal;
means for combining (75) a processed version of the analog main signal (output of 180 in Figure 1; or output of 54 in Figure 2) with a processed version of the analog predistortion signal (output of 66 in Figure 1; or output of 64 in Figure 2), to create an analog combined signal, the means for combining being disposed in the main signal path; and
means for amplifying (80) the analog combined signal, the means for amplifying being disposed in the main signal path.
However, McLaurin does not disclose a means for filtering the analog combined signal to generate a filtered version of the analog combined signal. FIG. 3 of Braithwaite discloses a means for filtering (240) a combined signal from a main signal path (203) and a predistortion path (205) wherein the filtered signal is amplified via a power amplifier (242). Since FIG. 4 of Asuri et al. discloses a predistortion transmitter that filters (via 322) a signal prior to mixing/modulating (via 324) the signal for input to a power amplifier (326 and 340), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to a means for filtering the analog combined signal in McLaurin prior to modulator 85 in order to limit the bandwidth of the signal to the assigned channel for transmission. (See Braithwaite, column 7, line 66 – column 8, line 6) Reversing or rearranging the order of a mixer and a filter is an obvious modification does not affect the functionality of the components themselves. (See also MPEP 2144.04(VI))
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over McLaurin in view of Braithwaite and Asuri et al. as applied to claim 13 above, and further in view of Wloczysiak. McLaurin in view of Braithwaite and Asuri et al. disclose the claimed invention except for the second DAC having a wider bandwidth than the first DAC. Wloczysiak teaches that a DAC in a predistortion path (i.e. the “second DAC”) must be configured to expanded bandwidth requirements compared to the DAC in a main signal (i.e. the “first DAC”) in order to successfully operate on the signals generated by the DPD in the predistortion path. (See column 6, line 58 – column 7, line 1) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use second DAC in wideband converter 60 that has a wider bandwidth than the first DAC in narrowband converter 50 in order to successfully operate on the predistortion signals to compensate for the non-linearity of the power amplifier.
Claim 17 is also rejected under 35 U.S.C. 103 as being unpatentable over Rexberg et al. in view of Asuri and Braithwaite as applied to claim 13 above, and further in view of Wloczysiak. Rexberg et al. in view of Asuri and Braithwaite disclose the claimed invention except for the second DAC having a wider bandwidth than the first DAC. Wloczysiak teaches that a DAC in a predistortion path (i.e. the “second DAC”) must be configured to expanded bandwidth requirements compared to the DAC in a main signal (i.e. the “first DAC”) in order to successfully operate on the signals generated by the DPD in the predistortion path. (See column 6, line 58 – column 7, line 1) Since Rexberg et al. discloses the bandwidth of the predistortion signal being wider than the bandwidth of the main signal (see Fig. 2 and column 2, lines 55-60), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use second DAC in the predistortion path (B-branch) of Rexberg et al. in view of Asuri and Braithwaite that has a wider bandwidth than the first DAC in order to successfully operate on the predistortion signals to compensate for the non-linearity of the power amplifier.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Please note that non-cited portions of the respective references may also read on the claim limitations. Therefore, the references should be considered in their entirety.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Betsy Deppe whose telephone number is 571-272-3054. The examiner can normally be reached Monday, Wednesday and Thursday, 7:00 am - 3:00 pm (ET).
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/BETSY DEPPE/Primary Examiner, Art Unit 2633
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