Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-4, 6-8, 11,12,14, and 19-21, is/are rejected under 35 U.S.C. 103 as being unpatentable over to CN111031011 and CN102123275 both sited by Applicant in IDS filed on 02/24/2025.
It has been noted that, a claimed invention is unpatentable if the differences between it and the prior art are "such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art." 35 U.S.C. § 103(a) (2000); KSRInt'lr. Teleflex Inc., 127 S.Ct. 1727, 1734 (2007); Graham v.John Deere Co., 383 U.S. 1, 13-14 (1966).
In Graham, the Court held that that the obviousness analysis is bottomed on several basic factual inquiries: "[(1)] the scope and content of the prior art are to be determined; [(2)] differences between the prior art and the claims at issue are to be ascertained; and [(3)] the level of ordinary skill in the pertinent art resolved." 383 U.S. at 17. See also KSR, 127 S.Ct. at 1734. "The combination of familiar elements according to known methods is likely to be obvious when it does no more; than yield predictable results." KSR, at 1739.
"When a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or in a different one. If a person of ordinary skill in the art can implement a predictable variation, § 103 likely bars its patentability." Id. at 1740.
"For the same reason, if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill." Id.
"Under the correct analysis, any need or problem known in the field of endeavor at the time of invention and addressed by the patent can provide a reason for combining the elements in the manner claimed." Id. 11742.
As per claims 1, 19, and 20, CN111031011 discloses a communication method applied to a data sending device ([0051-0052], further see English translation included by Examiner), characterized in comprising :in response to determining that there is data to be sent a (TCP connection is established between a host and a TCP/IP accelerator, [0051-0052]), calling a target interface to move the data to be sent into a target storage area (CN111031011 - data is transferred from the host end to a TCP/IP accelerator board, and data information can be read from the accelerator board. A TCP connection to the TCP/IP accelerator board is established, and configuration information is sent by means of a PIO read/ write mode of PCIE), wherein the target storage area is a storage area pre- allocated on a double data rate (CN111031011 - Data is read from the preset DDR module data storage address of the target TCP/IP accelerator board by means of the DMA read/write mode.) synchronous dynamic random access memory of a target accelerator card (CN111031011 - An address is allocated to target data, and a data write instruction is sent to the TCP/ IP accelerator board), the target accelerator card is a peripheral component interconnect express accelerator card (CN111031011 - A TCP connection to the TCP/IP accelerator board is established, and configuration information is sent by means of a PIO read/ write mode of PCIE), the data to be sent is data sent into a protocol stack of a transmission control protocol or an Internet interconnection protocol by a target application by calling a Socket interface function (CN111031011 - target data is written into a target TCP/IP accelerator board by means of a DMA read/write mode. The target data is stored in a preset data storage address in the target TCP/IP accelerator board.), and the target interface is configured for realizing communication between the protocol stack and the target accelerator card;( CN111031011 - After the TCP/IP accelerator board processes the target data, a data read instruction is sent to the TCP/ IP accelerator board. Data is read from the preset DDR module data storage address of the target TCP/IP accelerator board by means of the DMA read/write mode.
CN111031011 does not expressly disclose “calling the target interface to send a notification to a data receiving device, wherein the notification is configured for representing that the data to be sent has been stored in the target storage area.”
Nonetheless, CN102123275 discloses data to be send has been placed in a target storage region is indicted by sending/receiving a notification. Specifically, CN102123275 discloses having a video signal decoder, a video data rearrangement device, an on-board memory, and a PCIE-DMA controller arc provided on an I/O board that is inserted in a video data processing host device. The video signal decoder decodes a video signal in a signal source, arranges interleaved video data into block video data, and transfers the same to the on-board memory for storage. The notification happens when the I/O board sends a data preparation ready notification to an application in the video data processing host device. The application provides, to a board driving program, a memory address of the video data processing host prepared in advance by the application. The board driving program sends block video data of a complete video image frame from the on-board memory to a memory of the video data processing host by means of the PCIE-DMA controller and a system bus. (CN102123275, [0009-0042])
Therein, it would have been obvious to one of ordinary skill in the art before the effective filing date to further modify CN111031011 to incorporate a ready notification to an application of CN102123275 because doing so would add flexibility by improving the processing capacity of CN111031011’s system.
As per claims 2-4, CN111031011-CN102123275, teaches wherein the data sending device is a host, the target accelerator card is provided in the host, and the data receiving device is the target accelerator card; and the calling a target interface to move the data to be sent to a target storage area comprises: calling the target interface to move the data to be sent to the target storage area by direct memory access. (CN111031011 - target data is written into a target TCP/IP accelerator board by means of a DMA read/write mode. The target data is stored in a preset data storage address in the target TCP/IP accelerator board.),
As per claims 6-8, 21, and 22, CN111031011-CN102123275, teaches wherein the target interface is configured for realizing communication between a protocol stack of transmission control protocol or Internet interconnection protocol and the target accelerator card. See the rejection for claim 1.
As per claims 11, 12, and 14, see the rejection for claim 1.
Allowable Subject Matter
Claims 5, 9, 10, 13, 15, and 16, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c). 3. The following references Gao (US 12,074,931) shows video signal decoder decodes a video signal in a signal source and notification signals. (Abstract)
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMARA R PEYTON whose telephone number is (571)272-4157. The examiner can normally be reached on 9am-5pm, EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAMMARA R PEYTON/Primary Examiner, Art Unit 2184 January 24, 2026