DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Acknowledgment is made of applicant' s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
Page 16, last line: Delete the last line as it’s unnecessary to have.
Appropriate correction is required.
Drawings
The drawings are objected for failing to comply with PCT Rule 11.13(a), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. When zooming into the drawings, pixelation of the lines, numbers, and characters can be seen. This is a sign that the drawings were drawn in a color other than black, or the drawings were expanded past their native resolution.
The drawings are objected to because of the following informalities:
Fig. 1: Remove the reference character “100” as there is no reference to this character in the specification and does not seem to be referencing anything different compared to reference character “102”
Fig. 3: The boxes around each element 310, 320, and 330, vary between having a solid line, having a dashed line, or having no line. Applicant is advised to use a solid line for each of the boxes.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 12 and 21 are objected to because of the following informalities:
Claim 12, line 1: Insert “one or more” before “vector instructions” to maintain consistency with the language used in claim 11.
Claim 21, lines 10-11: Remove the repeated phrase “reinterpreting the one or more vector instructions as matrix instructions”.
Appropriate correction is required.
Claim Interpretation
Claims 21 recites the limitation “one or more computer storage media” in line 1. As per Applicant’s specification in page 14, lines 15-16, it states “the computer storage medium is not, however, a propagated signal.” Therefore, Examiner will not interpret the limitation to be including signals per se. Examiner recommends that Applicant explicitly states “non-transitory” before “computer” to remove any ambiguity in which the limitation comprises.
The following is a quotation of MPEP 2111.04(II):
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.
The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.
Claim 11 recites the contingent limitation “based on information set in the configuration register” in line 7. The limitation suggests, under BRI, that if the “information set in the configuration register” is not the information expected, the reinterpreting of one or more vector instructions as matrix instructions does not occur. In the case that the claim becomes allowable, over the prior art, Applicant is advised to insert “positively occurring” actions within the method claim so that the conditional of the contingent limitations may be satisfied and recites the same invention as the independent processor claim and independent computer storage media claim. Note that this does not indicate that the claim is allowable and should not be interpreted in that regard.
Claims 12-14 contain limitations which are contingent on the “information set in the configuration register” containing the expected information.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9 and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Per MPEP 2164.01(a), there are many factors to be considered when determining whether there is sufficient evidence to support a determination that a disclosure does not satisfy the enablement requirement and whether any necessary experimentation is “undue.” These factors include, but are not limited to:
The breadth of the claims;
The nature of the invention;
The state of the prior art;
The level of one of ordinary skill;
The level of predictability in the art;
The amount of direction provided by the inventor;
The existence of working examples; and
The quantity of experimentation needed to make or use the invention based on the content of the disclosure.
In re Wands, 858 F.2d 731, 737, 8 USPQ2d 1400, 1404 (Fed. Cir. 1988)
Claim 9 encompasses a field of a configuration register representing a horizontal accumulation span (Factor A). The nature of the invention of claims 1 and 9 is to reinterpret one or more vector instructions as matrix instructions in response to a configuration register being set by an instruction executed by a processor, in which a field of the configuration register represents a horizontal accumulation span value that a processor is to interpret as a directed to use a pre-add instruction during a multiply-accumulate operation (Factor B). However, Applicant has not explained how the pre-add instruction would be used during a multiply-accumulate operation or specify how exactly the instruction is to flow through a processor’s pipeline. On page 12, lines 16-27, the specification merely states that a value of the horizontal accumulation span is to be used as a direction to use a pre-add instruction during a multiply-accumulate operation, without any further detail on how this instruction is to be used or implemented in the processor during the multiply-accumulate operation. Additionally, Applicant use the terms “instruction” and “operation” interchangeably, which further obfuscates what the pre-add element is supposed to be. Therefore, one of ordinary skill in the art would not understand how to insert the instruction during a multiply-accumulate operation, without undue experimentation, given the short specification that does not provide direction, drawings, or working examples for this embodiment (Factors D, F, G, H). Although the computer arts are generally predictable, this general predictability does not allow one to fill in the blanks left by Applicant to be able to insert the pre-add instruction (Factor E). The prior art, none of which can be used in a rejection, does not serve to assist in enabling this invention (Factor C). Consequently, the examiner asserts that the totality of evidence suggests that Applicant has not enabled one of ordinary skill to make/use the invention of claim 1 to use a pre-add instruction during a multiply-accumulate operation (as set forth in claim 9).
Claim 19 is similar in scope to claim 9. Therefore, the same reasons apply to claim 19.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 4, 11-17, and 19-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the vector instructions" in line 2. There is insufficient antecedent basis for this limitation in the claim. There was no prior instance of “vector instructions” within the claim or the claim it depends on. Only “one or more vector instructions was established in claim 1. For the sake of examination, Examiner will interpret this limitation to be “the one or more vector instructions”.
Claim 4 recites the limitation "the vector register" in line 2. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the limitation is referring to “a vector register” in claim 4, line 1, or “a vector register “ in claim 3, lines 2-3. For the sake of examination, Examiner will interpret this limitation to be referring to both instances of “a vector register’ (i.e., both instances are referring to the same “vector register”).
Claim 14 is rejected for the same reasons as claim 4.
Claim 11 recites the limitation "the instruction" in line 5. There is insufficient antecedent basis for this limitation in the claim. It’s not clear if the limitation is referring to one of the “instructions” set forth in claim 11, line 3, or referring to “an instruction” in claim 11, line 2. For the sake of examination, Examiner will change “an instruction” in claim 11, line 2 to be “a configuration instruction” and “the instruction” in claim 11, line 5 to be “”the configuration instruction”.
Claims 12-17 and 19-20 are rejected for inheriting the rejection of claim 11.
Claim 15 recites the limitation "the instruction" in line 2. There is insufficient antecedent basis for this limitation in the claim. It’s not clear if the limitation is referring to one of the “instructions” set forth in claim 11, line 3, or referring to “a configuration instruction” in claim 11, line 2. For the sake of examination, Examiner will interpret this limitation to be referencing to “a configuration instruction” in claim 11, line 2.
Claim 16 is rejected for inheriting the rejection of claim 15.
Claim 17 recites the limitation "the instruction" in line 2. There is insufficient antecedent basis for this limitation in the claim. It’s not clear if the limitation is referring to one of the “instructions” set forth in claim 11, line 3, or referring to “a configuration instruction” in claim 11, line 2. For the sake of examination, Examiner will interpret this limitation to be referencing to “a configuration instruction” in claim 11, line 2.
Claim 19 recites the limitation "the instruction" in line 2. There is insufficient antecedent basis for this limitation in the claim. It’s not clear if the limitation is referring to one of the “instructions” set forth in claim 11, line 3, or referring to “a configuration instruction” in claim 11, line 2. For the sake of examination, Examiner will interpret this limitation to be referencing to “a configuration instruction” in claim 11, line 2.
Claim 21 recites the limitation "the instruction" in line 7. There is insufficient antecedent basis for this limitation in the claim. It’s not clear if the limitation is referring to one of the “instructions” set forth in claim 21, line 1 or lines 3-4, or referring to “an instruction” in claim 21, line 2. For the sake of examination, Examiner will change “an instruction” in claim 21, line 2 to be “a configuration instruction” and “the instruction” in claim 21, line 7 to be “”the configuration instruction”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-17 and 19-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claims 1, 11, and 21 are a processor claim, a method claim, and computer storage media claim, respectively. Therefore, claims 1, 11, and 21 are directed to a process, machine, manufacture or composition of matter.
Under Prong One of Step 2A of the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), claim 1 recites “one or more values… to reinterpret one or more vector instructions as matrix instructions” Such limitations cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The elements “a processor configured to implement an instruction set architecture” and “an instruction that in operation sets a configuration register of the processor with one or more values” are recited at a high level of generality, which amount to no more than mere instructions to apply the exception (MPEP 2105.05(f)). Thus, the elements fail to integrate the judicial exception into a practical application.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously, with respect to Step 2A Prong Two, the elements amount to no more than mere instructions to apply the exception using elements recited at a high level (MPEP 2105.05(f)). Accordingly, this claim is not patent-eligible under 35 U.S.C. 101.
Regarding claim 2, the claim recites “perform vector arithmetic on a sequence of matrices”. The limitation further convers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and mathematical concepts such as mathematical relationships, mathematical formulas/equations, or mathematical calculations. The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 3, the claim recites “reinterpreting data as a sequence of matrices”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The element “vector registers” is recited at a high level of generality, which amount to no more than mere instructions to apply the exception (MPEP 2105.05(f)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 4, the claim recites “reinterpreting the data as a sequence of 2x2, 4x4, 8x8, or 16x16 matrices”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 5, the claim recites “a field representing a matrix width”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 6, the claim recites “the matrix width represents an exponent N for a matrix having a width given by 2^N”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 7, the claim recites “a field representing a matrix data order”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 8, the claim recites “a field representing a widening mode”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 9, the claim recites “a field representing a horizontal accumulation span”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim also recites “interpret a value of the horizontal accumulation span as a directed to use a pre-add instruction during a multiply-accumulate operation” The limitation further convers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and mathematical concepts such as mathematical relationships, mathematical formulas/equations, or mathematical calculations. The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 10, the claim recites “a bit… interpret the one or more vector instructions to be referencing vector inputs or matrix inputs”. The limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The element “second different configuration register” is recited at a high level of generality, which amount to no more than mere instructions to apply the exception (MPEP 2105.05(f)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Regarding claim 11-17 and 19-20, the claims recite a method similar to the processor of claims 1-7 and 9-10, respectively. Therefore, the claims are rejected on the same premises.
Regarding claim 21, the claim is mostly rejected for the same reasons as claim 1. The claim also recites “one or more computer storage media encoded with instructions”. The element is recited at a high level of generality, which amount to no more than mere instructions to apply the exception (MPEP 2105.05(f)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-8, 10-17, and 20-21 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Adelman et al. (US 20210406018 A1).
“Intel Architecture Instruction Set Extensions and Future Features Programming Reference” (hereinafter Intel) is cited as extrinsic evidence to provide additional details of the TILECONFIG/LDTILECONFIG instruction.
Wikipedia “Control register” is cited as extrinsic evidence to provide details of the XCR0 register.
Regarding claim 1, Adelman teaches a processor (Fig. 18: Processor/core 1805) configured to implement an instruction set architecture ([0128]: Many of the exemplary cores in the specification support the x86 instruction set) having an instruction ([0065, 0151]: TILECONFIG (or also known as LDTILECONFIG) is an instruction that changes the tile configurations) that in operation sets a configuration register of the processor with one or more values (Fig. 18 and [0151-0153]: The TILECONFIG instruction fetches a tile description comprising of tile configurations, which is then stored in register(s) 1819 (Which may include just being a single register). Since the register store tile configurations, it’s a configuration register) that cause the processor to reinterpret one or more vector instructions as matrix instructions (Fig. 18 and [0151-0153]: The TILECONFIG instruction fetches bytes of data from memory, in which these bytes indicate the bytes per row (i.e., number of columns) and number of rows. Therefore, there exists an initial configuration when all tiles are either 1xN, Nx1, or a mix of the two, effectively making them vectors. This turns arithmetic tile instructions, such as TDPBF16PS (A tile instruction in x86, see Intel, page 105) into vector instructions for only being able to intake 1xN, Nx1, or a mix of the two vector types. Then, the processor can reinterpret the vector instructions as matrix instructions when the TILECONFIG instruction sets register(s) 1819, which sets the tiles to be either NxM or NxN matrices (see Intel, page 100)).
Regarding claim 2, Adelman teaches the processor of claim 1, wherein the processor is configured to perform vector arithmetic on a sequence of matrices to reinterpret the vector instructions as matrix instructions ([0151-0153]: When the TILECONFIG instruction sets the tiles to be NxM or NxN, the TDPF16PS instruction, for example, performs SIMD dot-products of each possible combination of rows and columns of a first matrix and second matrix, respectively (see Intel, page 105). Therefore, the processor performs vector arithmetic on a sequence of matrices (i.e., the first matrix and second matrix), which reinterprets the vector instructions as matrix instructions).
Regarding claim 5, Adelman teaches the processor of claim 1, wherein the configuration register has a field representing a matrix width ([0151-0153]: The tilex.colsb field in the register storing the tile configuration information would include indicating how many bytes are in each row of a tile (e.g., tile0.colsb indicates the number of bytes in each row of tile 0) (see Intel, page 100). The number of bytes in a row of a tile as the matrix width).
Regarding claim 6, Adelman teaches the processor of claim 5, wherein the field representing the matrix width represents an exponent N for a matrix having a width given by 2^N ([0151-0153]: When the tilex.colsb field in the register storing the tile configuration information is set to a value 4, for example, the width of the tile comprising a matrix would be 4 bytes, i.e., 2^2 bytes. In other words, the value 4 represents an exponent N=2).
Regarding claim 7, Adelman teaches the processor of claim 1, wherein the configuration register has a field representing a matrix data order ([0151-0153]: The tile configuration register includes the start_row field, which indicates the row to begin fetching data from for execution (i.e., a matrix data order)).
Regarding claim 8, Adelman teaches the processor of claim 1, wherein the configuration register has a field representing a widening mode ([0151-0153]: The tilex.colsb field in the register storing the tile configuration information would include indicating how many bytes are in each row of a tile. Therefore, a number bigger than one would be widening the tiles. Hence, the tile configuration information including a field indicating how many bytes are in each row of a tile represents a widening mode when the field indicates a value bigger than one).
Regarding claim 10, Adelman teaches the processor of claim 1, wherein the instruction set architecture specifies an enable bit in a second different configuration register (The x86 architecture refers to an XCR0 register, which is a feature-enabling/control register (i.e., a configuration register) (See Wikipedia, page 5, under “XCR0 and XSS”). Bits 17-18 of the XCR0 register indicates the enabling of features of the AMX extension (referring to the tile registers and tile instructions). Bit 18 of the XCR0 register as an enable bit in a second different register) that specifies whether the processor will interpret the one or more vector instructions to be referencing vector inputs or matrix inputs (If bit 18 of XCR0 is not set, the instructions corresponding to AMX cannot be executed. Therefore, the processor will not be able to interpret the one or more tile instructions to be referencing vector inputs or matrix inputs since the tile instructions cannot be executed (see Intel, pages 96, Section 3.3 and pages 98-99)).
Regarding claim 11, Adelman teaches a method performed by a processor (Fig. 18: Processor/core 1805) implementing an instruction set architecture ([0128]: Many of the exemplary cores in the specification support the x86 instruction set) having an instruction ([0065, 0151]: TILECONFIG (or also known as LDTILECONFIG) is an instruction that changes the tile configurations) for setting a configuration register of the processor (Fig. 18 and [0151-0153]: The TILECONFIG instruction fetches a tile description comprising of tile configurations, which is then stored in register(s) 1819 (Which may include just being a single register). Since the register store tile configurations, it’s a configuration register) that controls whether vector instructions are reinterpreted as matrix instructions ([0151-0153]: The TILECONFIG instruction fetches bytes of data from memory, in which these bytes indicate the bytes per row (i.e., number of columns) and number of rows. Therefore, there exists an initial configuration when all tiles are either 1xN, Nx1, or a mix of the two, effectively making them vectors. This turns arithmetic tile instructions, such as TDPBF16PS (A tile instruction in x86, see Intel, page 105) into vector instructions for only being able to intake 1xN, Nx1, or a mix of the two vector types. Then, the processor can reinterpret the vector instructions as matrix instructions when the TILECONFIG instruction sets the tiles to be either NxM or NxN matrices (see Intel, page 100)), the method comprising:
executing the instruction to set the configuration register (Fig. 18 and [0151-0153]: The processor/core 1805 is able to execute the TILECONFIG instruction, which sets register(s) 1819);
receiving one or more vector instructions (Fig. 18 and [0128]: Since many of the exemplary cores in the specification support the x86 instruction set and the processor/core 1805 supports tiles, the processor/core 1805 may receive tile instructions such as TDPBF16PS); and
based on information set in the configuration register, reinterpreting the one or more vector instructions as matrix instructions (Fig. 18 and [0151-0153]: There exists an initial configuration when all tiles are either 1xN, Nx1, or a mix of the two, effectively making them vectors. This turns arithmetic tile instructions, such as TDPBF16PS, into vector instructions for only being able to intake 1xN, Nx1, or a mix of the two vector types. Then, the processor can reinterpret the vector instructions as matrix instructions when the TILECONFIG instruction sets register(s) 1819, which sets the tiles to be either NxM or NxN matrices (see Intel, page 100)).
Claims 12-14 are rejected for the same reasons as claim 11 because, as discussed in the “Claim Interpretation” section, the limitations of claim 11 are contingent and not required.
Regarding claims 12, 15-17 and 20, the claims recite a method similar to the processor of claims 2, 5-7, and 10, respectively. Therefore, the claims are rejected on the same premises.
Regarding claim 21, the claim is mostly rejected for the same reasons as claim 11. Adelman also teaches one or more computer storage media encoded with instructions of an instruction set architecture (Figs. 13 and 18, [0122]: Core 1390 is an exemplary pipeline embodiment of a core of a processor (which would include processor/core 1805), which comprises of an instruction storage 1301 to store (i.e., encoded with) instructions that may correspond to the x86 instruction set architecture. Instruction storage as the computer storage media).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Adelman et al. (US 20210406018 A1) in view of Mansell et al. (WO 2019002811 A1).
Regarding claim 3, Adelman teaches the processor of claim 1, wherein reinterpreting a vector instruction as a matrix instruction comprises reinterpreting data in a vector register as ([0151-0153]: The registers used in instructions such as TDPBF16PS are vector registers for initially being able to store the 1xN or Nx1 vectors before reconfiguring the tiles to be NxM or NxN registers).
Adelman does not teach that the data in the vector registers are reinterpreted as a sequence of matrices.
Mansell teaches to interpret data in vector registers as a sequence of matrices (Fig. 7A, page 25, line 27 to page 26, line 9: The 512-bit vector register 50 comprises of 4 2x2 matrices in sequence).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Adelman with the teachings of Mansell to have the data in the registers be interpreted as a sequence of matrices. Each smaller matrix can represent different types of data, which allows a register to hold four types of data at a time, which may be appreciated by one of ordinary skill.
Regarding claim 4, Adelman, in view of Mansell, teaches the processor of claim 3, wherein reinterpreting the data in a vector register as a sequence of matrices comprises reinterpreting the data in the vector register as a sequence of 2x2, 4x4, 8x8, or 16x16 matrices (Mansell, Fig. 7A: In the current combination, the data stored in the vector register comprises of a sequence of 2x2 matrices).
Regarding claims 13-14, the claims recite a method similar to the processor of claims 3-4, respectively. Therefore, the claims are rejected on the same premises.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20100115233 A1: Brewer et al. teaches a processor in which the processor partitions vector registers based on a partitioning mode
US 9081564 B2: Reid teaches a processor that reinterprets certain scalar instructions into vector instructions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ALCANTARA-RAMOS whose telephone number is (571)272-4211. The examiner can normally be reached Mon-Fri 8:30-5:00 PST.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
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