DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The preliminary amendment filed 11/26/2024 is acknowledged and made of record. Claims 1-20 are now pending.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed 05/16/2025 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
The information disclosure statement 05/16/2025 is being considered in part by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9, recites “wherein transistors in the pre-stage driving circuit are P-type transistors…” however, there is no recitation of the pre-stage comprising transistors as implied by this limitation. There is insufficient antecedent basis for this limitation in the claim.
Claim 15, recites “wherein transistors in the pixels…” however, there is no recitation of the pixels comprising transistors as implied by this limitation. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 13-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Guo et al. (US 20260073834)
As to Claim 1, Guo et al. discloses A shift register unit, comprising: a pre-stage driving circuit (fig.1-7; first control module 110 and second control module 120, collectively) respectively connected to a driving control terminal (fig.1-7; terminal SIN, SCK3, SCK1, SCK2), a first power supply terminal (fig.1-7, VGH), a second power supply terminal (fig.1-7; VGL), and a pre-stage output terminal (fig.1-7, output node N2, N1), and configured to control switching on and off of a connection between the first power supply terminal and the pre-stage output terminal (fig.1-7; para.0039, 0041), and switching on and off of a connection between the second power supply terminal and the pre-stage output terminal based on a driving control signal provided by the driving control terminal (fig.1-7; para.0042); and
a post-stage control circuit (fig.1-7, output module 130) respectively connected to the pre-stage output terminal (fig.1-7; nodes N2, N1), an output control terminal (fig.1-7, terminals SCK2, VGH), and a post-stage output terminal (fig.1-7; output terminal OUT), wherein the post- stage output terminal is configured to be connected to pixels in a display panel (fig.10,14; para.0096, 0119), and
the post-stage control circuit is configured to: control a connection between a first terminal and the post-stage output terminal to be switched on based on a pre- stage signal from the pre-stage output terminal and an output control signal provided by the output control terminal, so that the pre-stage signal is transmitted from the first terminal to the post-stage output terminal (fig.1-7, para.0043, output module 130, based on level of node N1, the clock signal SCK2 to be transmitted to output terminal OUT and based on the level of the second node N2, the first level signal VGH to be transmitted to the output terminal OUT of the shift register), the terminal is one of the pre-stage output terminal and the output control terminal (para.0043, output node N1, N2 (pre-stage output terminal) and VGH (output control terminal)) and a potential of the transmitted output control signal is not less than a potential of a first power supply signal provided by the first power supply terminal (para.0043,0048; VGH).
As to Claim 13 has limitations similar to those of Claim 1 and are met by the reference as set forth above.
As to Claim 14 has limitations similar to those of Claim 1 and are met by the reference as set forth above. Claim 14, further recites: “a display panel (fig.10, para.0096 ), and a gate driving circuit comprising at least two cascaded shift-register units (fig.10, 14-shift register 50); wherein the display panel comprises a plurality of pixels (fig.10, pixel circuits 1), and the gate driving circuit is connected to the plurality of pixels and configured to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light (fig.10, para.0096).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US 20260073834) in view of Yuan et al. (US 2019/0103166).
As to Claim 7, Guo et al. discloses wherein the driving control terminal comprises a first clock terminal (fig.1-7, SCK3), a second clock terminal (fig.1-7, SCK2), a start signal terminal (fig.1-7, initial signal SIN) and a potential control terminal; the pre-stage driving circuit is configured to control the switching on and off of the connection between the first power supply terminal and the pre-stage output terminal and the switching on and off of the connection between the second power supply terminal and the pre- stage output terminal based on a first clock signal provided by the first clock terminal, a second clock signal provided by the second clock terminal, a start signal provided by the start signal terminal, a potential control signal provided by the potential control terminal, the first power supply signal and a second power supply signal provided by the second power supply terminal (fig.1-7; para.0039,041).
Guo et al. does not expressly disclose a potential control terminal.
Yuan et al. discloses a shift register unit comprising a timing control TC terminal (fig.10), where the timing control terminal signal end TC may control the voltage applied to the second pull-up node P2 based on the voltage applied to the first pull-up node P1 (para.0040-0041, 0082).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Guo et al. with the teachings of Yuan et al., the motivation being to control a time point when the output circuit enters a desired operating state.
Claim(s) 9, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US 20260073834) in view of Cao et al. (US 20240257781).
As to Claim 9, Guo et al. discloses wherein transistors in the pre-stage driving circuit are P-type transistors (fig.2,5-7; para.0046), and a material of the P- type transistor comprises low temperature poly-silicon; wherein the potential of the first power supply signal provided by the first power supply terminal is greater than a potential of a second power supply signal provided by the second power supply terminal (fig.1-7; VGH is higher than VGL; para.0047-0048).
Guo et al. does not expressly disclose, but Cao et al. discloses: a material of the P- type transistor comprises low temperature poly-silicon (para.0026,0032-0033).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Guo et al. with the teachings of Cao et al., the motivation being to facilitate fast pull-down and fast pull-up capability of the gate driver.
As to Claim 15, Guo et al. discloses pixel circuits (1), but does not expressly disclose, but Cao discloses: wherein transistors in the pixels are N-type transistors, and a material of the N-type transistor comprises an oxide material (fig.1, para.0028-0029, pixel circuit 30 comprises switching transistor K, that may be N-type metal oxide thin film).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Guo et al. with the teachings of Cao et al., the motivation being to reduce a leakage current of the switching transistor during display process and meet a requirement of a long screen duration in the low-frequency or ultra-low-frequency display process.
Allowable Subject Matter
Claims 2-6, 8, 10-12, 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is allowable over the prior art of record since the cited references alone or in combination do not teach or suggest “wherein a switch-on duration of the connection between the first power supply terminal and the pre-stage output terminal is less than a switch-on duration of the connection between the second power supply terminal and the pre-stage output terminal; the output control terminal comprises a first output control terminal and a second output control terminal, wherein a potential of an output control signal provided by the second output control terminal is not less than the potential of the first power supply signal; and the post-stage control circuit is configured to control switching on and off of a connection between the pre-stage output terminal and the post-stage output terminal based on the pre- stage signal and an output control signal provided by the first output control terminal, and control a connection between the second output control terminal and the post-stage output terminal to be switched on upon controlling the connection between the pre-stage output terminal and the post-stage output terminal to be switched off” in combination with the other limitations in the claim.
Claim 8 is allowable over the prior art of record since the cited references alone or in combination do not teach or suggest “wherein the pre-stage driving circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a first capacitor, a second capacitor and a third capacitor; wherein a gate electrode of the first transistor is connected to the first clock terminal, a first electrode of the first transistor is connected to the start signal terminal, and a second electrode of the first transistor is connected to a first node; a gate electrode of the second transistor is connected to the first node, a first electrode of the second transistor is connected to the first clock terminal, and the first electrode of the second transistor is connected to a second node; a gate electrode of the third transistor is connected to the first clock terminal, a first electrode of the third transistor is connected to the second power supply terminal, and a second electrode of the third transistor is connected to the second node; a gate electrode of the fourth transistor is connected to a tenth node, a first electrode of the fourth transistor is connected to the second clock terminal, and a second electrode of the third transistor is connected to a fifth node; a gate electrode of the fifth transistor is connected to the second node, a first electrode of the fifth transistor is connected to the first power supply terminal, and a second electrode of the fifth transistor is connected to the fifth node; a gate electrode of the sixth transistor is connected to a sixth node, a first electrode of the sixth transistor is connected to the second clock terminal, and a second electrode of the sixth transistor is connected to a third node; a gate electrode of the seventh transistor is connected to the second clock terminal, a first electrode of the seventh transistor is connected to the third node, and a second electrode of the seventh transistor is connected to a fourth node; a gate electrode of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to the first power supply terminal, and a second electrode of the eighth transistor is connected to the fourth node; a gate electrode of the ninth transistor is connected to the fourth node, a first electrode of the ninth transistor is connected to the first power supply terminal, and a second electrode of the ninth transistor is connected to the pre-stage output terminal; a gate electrode of the tenth transistor is connected to a seventh node, a first electrode of the tenth transistor is connected to the second power supply terminal, and a second electrode of the tenth transistor is connected to the pre-stage output terminal; a gate electrode of the eleventh transistor is connected to the second power supply terminal, a first electrode of the eleventh transistor is connected to the second node, and a second electrode of the eleventh transistor is connected to the sixth node; a gate electrode of the twelfth transistor is connected to the second power supply terminal, a first electrode of the twelfth transistor is connected to the first node, and a second electrode of the twelfth transistor is connected to the seventh node; a gate electrode of the thirteenth transistor is connected to the potential control terminal, a first electrode of the thirteenth transistor is connected to the first power supply terminal, and a second electrode of the thirteenth transistor is connected to the first node; a gate electrode of the fourteenth transistor is connected to the first clock terminal, a first electrode of the fourteenth transistor is connected to the start signal terminal, and a second electrode of the fourteenth transistor is connected to an eighth node; a gate electrode of the fifteenth transistor is connected to the second power supply terminal, a first electrode of the fifteenth transistor is connected to the eighth node, and a second electrode of the fifteenth transistor is connected to a ninth node; a gate electrode and a first electrode of the sixteenth transistor are both connected to the ninth node, and a second electrode of the sixteenth transistor is connected to the seventh node; and one terminal of the first capacitor is connected to the sixth node, and the other terminal of the first capacitor is connected to the third node; one terminal of the second capacitor is connected to the fourth node, and the other terminal of the second capacitor is connected to the first power supply terminal; and one terminal of the third capacitor is connected to the fifth node, and the other terminal of the third capacitor is connected to the ninth node” in combination with the other limitations in the claim.
Claim 10 is allowable over the prior art of record since the cited references alone or in combination do not teach or suggest “…if a potential of the pre-stage signal from the pre-stage output terminal is less than a potential threshold, controlling, by the post-stage control circuit, a connection between the pre- stage output terminal and the post-stage output terminal to be switched on based on the pre- stage signal and the output control signal provided by the output control terminal, so that pre-stage signal is transmitted from the pre-stage output terminal to the post-stage output terminal; and if the potential of the pre-stage signal is greater than the potential threshold, controlling, by the post-stage control circuit, a connection between the output control terminal and the post- stage output terminal to be switched on based on the pre-stage signal and the output control signal provided by the output control terminal, so that the output control signal is transmitted from the output control terminal to the post-stage output terminal, and the potential of the transmitted output control signal is not less than the potential of the first power supply signal; wherein the potential threshold is between the potential of the first power supply signal and a potential of a second power supply signal provided by the second power supply terminal” along with the other limitations in the claim.
Claim 16 is allowable over the prior art of record since the cited references alone or in combination do not teach or suggest “wherein a switch-on duration of the connection between the first power supply terminal and the pre-stage output terminal is less than a switch-on duration of the connection between the second power supply terminal and the pre-stage output terminal; the output control terminal comprises a first output control terminal and a second output control terminal, wherein a potential of an output control signal provided by the second output control terminal is not less than the potential of the first power supply signal; and the post-stage control circuit is configured to control switching on and off of a connection between the pre-stage output terminal and the post-stage output terminal based on the pre- stage signal and an output control signal provided by the first output control terminal, and control a connection between the second output control terminal and the post-stage output terminal to be switched on upon controlling the connection between the pre-stage output terminal and the post-stage output terminal to be switched off” along with the other limitations in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see PTO-892 form.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DISMERY MERCEDES/ Primary Examiner, Art Unit 2627
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