DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9, 17-18, 26, and 29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Tseng; Ying-Hsiang et al., US 20160217870 A1].
Regarding claim 1:
Tseng discloses:
1. (Original) A driving circuit [Tseng: Fig.1; ¶ 0019: “As shown in FIG. 1, a shift register unit is firstly provided in the present exemplary embodiment”], comprising
a first output circuit (11) [Tseng: Fig.1: fifth transistor T5],
a second output circuit (12) [Tseng: Fig.1: sixth transistor T6], and
a first output node control circuit (13) [Tseng: Fig.1: fourth transistor T4],
wherein a control end of the first output circuit (11) [Tseng: Fig.1: fifth transistor T5] is electrically connected to a first output node (NO1) [Tseng: Fig.1: second node N2; ¶ 0024: “ A control end of the fifth transistor T5 is coupled with the second node N2”], and
the first output circuit (11) [Tseng: Fig.1: fifth transistor T5] is further electrically connected to each of a first voltage end (V1) [Tseng: Fig.1: first voltage VDD; ¶ 0024: “a first end of the fifth transistor T5 is coupled with the first voltage VDD”] and
a driving signal output end (GT) [Tseng: Fig.1: signal output end VOUT; ¶ 0024: “a second end of the fifth transistor T5 is coupled with a signal output end VOUT”], and
configured to control the driving signal output end (GT) [Tseng: Fig.1: signal output end VOUT] to be electrically connected to or electrically disconnected from the first voltage end (V1) [Tseng: Fig.1: first voltage VDD] under the control of a potential of the first output node (NO1) [Tseng: Fig.1: second node N2; ¶ 0024: “When the potential of the second node N2 is a low level, the fifth transistor T5 turns on, and the first voltage VDD is output from the signal output end VOUT”];
a control end of the second output circuit (12) [Tseng: Fig.1: sixth transistor T6] is electrically connected to a second output node (NO2) [Tseng: Fig.1: first node N1; ¶ 0025: “ A control end of the sixth transistor T6 is coupled with a first end of the second capacitor C2”; ¶ 0026: “The first end of the second capacitor C2 is coupled with the first node N1”], and
the second output circuit (12) [Tseng: Fig.1: sixth transistor T6] is further electrically connected to each of an output signal end (S1) [Tseng: Fig.1: second clock signal CK2; ¶ 0025: “a first end of the sixth transistor T6 is coupled with a second clock signal CK2”] and
the driving signal output end (GT) [Tseng: Fig.1: signal output end VOUT; ¶ 0025: “a second end of the sixth transistor T6 is coupled with the signal output end VOUT”], and
configured to control the driving signal output end (GT) [Tseng: Fig.1: signal output end VOUT] to be electrically connected to or electrically disconnected from the output signal end (S1) [Tseng: Fig.1: second clock signal CK2] under the control of a potential of the second output node (NO2) [Tseng: Fig.1: first node N1; ¶ 0025: “When the voltage of the first end of the second capacitor C2 is a low level, the sixth transistor T6 turns on, and the second clock signal CK2 is output from the signal output end VOUT”];
the first output node control circuit (13) [Tseng: Fig.1: fourth transistor T4] is electrically connected to each of a first output control end (Tx1) [Tseng: Fig.1: first clock signal CK1; ¶ 0023: “A control end of the fourth transistor T4 is coupled with the first clock signal CK1”],
a second voltage end (V2) [Tseng: Fig.1: second voltage VEE; ¶ 0023: “a first end of the fourth transistor T4 is coupled with the second voltage VEE”], and
the first output node (NO1) [Tseng: Fig.1: second node N2; ¶ 0023: “A second end of the fourth transistor T4 is coupled with the second node N2”], and
configured to control the first output node (NO1) [Tseng: Fig.1: second node N2] to be electrically connected to or electrically disconnected from the second voltage end (V2) [Tseng: Fig.1: second voltage VEE] under the control of a first output control signal provided by the first output control end (Tx1) [Tseng: Fig.1: first clock signal CK1; ¶ 0023: “When the first clock signal CK1 is a low level, the fourth transistor T4 turns on, and the second voltage VEE is input to the second node N2”].
Regarding claim 2:
Tseng discloses:
2. (Original) The driving circuit according to claim 1, further comprising a second output node control circuit (21) [Tseng: Fig.1: second transistor T2],
wherein the second output node control circuit (21) [Tseng: Fig.1: second transistor T2] is electrically connected to each of a second output control end (Tx2) [Tseng: Fig.1: first clock signal CK1; ¶ 0021: “A control end of the second transistor T2 is coupled with a first clock signal CK1”],
a third voltage end (V3) [Tseng: Fig.1: first voltage VDD; ¶ 0021: “a first end of the second transistor T2 is coupled with a first voltage VDD”], and
the second output node (NO2) [Tseng: Fig.1: first node N1; ¶ 0021: “A second end of the second transistor T2 is coupled with the first node N1”], and
configured to control the second output node (NO2) [Tseng: Fig.1: first node N1]to be electrically connected to or electrically disconnected from the third voltage end (V3) [Tseng: Fig.1: first voltage VDD] under the control of a second output control signal provided by the second output control end (Tx2) [Tseng: Fig.1: first clock signal CK1; ¶ 0021: “When the first clock signal CK1 is a low level, the second transistor T2 turns on, and the first voltage VDD is input to the first node N1”; Claim 2 does not require the third voltage end or second output control end to differ from the first voltage end (V1) or first output control end (Tx1); under BRI both may read on VDD and CK1, respectively.].
Regarding claim 3:
Tseng discloses:
3. (Original) The driving circuit according to claim 1,
wherein the first output node control circuit (13) [Tseng: Fig.1: fourth transistor T4] comprises a first transistor (T1) [Tseng: Fig.1: fourth transistor T4];
a gate electrode of the first transistor (T1) [Tseng: Fig.1: fourth transistor T4] is electrically connected to the first output control end (Tx1) [Tseng: Fig.1: first clock signal CK1; ¶ 0023: “A control end of the fourth transistor T4 is coupled with the first clock signal CK1”],
a first electrode of the first transistor (T1) [Tseng: Fig.1: fourth transistor T4] is electrically connected to the second voltage end (V2) [Tseng: Fig.1: second voltage VEE; ¶ 0023: “a first end of the fourth transistor T4 is coupled with the second voltage VEE”], and
a second electrode of the first transistor (T1) [Tseng: Fig.1: fourth transistor T4] is electrically connected to the first output node (NO1) [Tseng: Fig.1: second node N2; ¶ 0023: “A second end of the second transistor T2 is coupled with the first node N1”].
Regarding claim 4:
Tseng discloses:
4. (Currently Amended) The driving circuit according to claim 2,
wherein the second output node control circuit (21) [Tseng: Fig.1: second transistor T2] comprises a second transistor (T2) [Tseng: Fig.1: second transistor T2];
a gate electrode of the second transistor (T2) [Tseng: Fig.1: second transistor T2] is electrically connected to the second output control end (Tx2) [Tseng: Fig.1: first clock signal CK1; ¶ 0021: “A control end of the second transistor T2 is coupled with a first clock signal CK1”],
a first electrode of the second transistor (T2) [Tseng: Fig.1: second transistor T2] is electrically connected to the third voltage end (V3) [Tseng: Fig.1: first voltage VDD; ¶ 0021: “a first end of the second transistor T2 is coupled with a first voltage VDD”], and
a second electrode of the second transistor (T2) [Tseng: Fig.1: second transistor T2] is electrically connected to the second output node (NO2) [Tseng: Fig.1: first node N1; ¶ 0021: “A second end of the second transistor T2 is coupled with the first node N1”] or [Examiner: Limitations recited in the alternative (“or”) and thus only one of the alternative limitations needs to be taught to anticipate the claim.],
wherein the first output control end (Tx1) [Tseng: Fig.1: first clock signal CK1] and the second output control end (Tx2) [Tseng: Fig.1: first clock signal CK1] are a same output control end [Tseng: ¶ 0023: “A control end of the fourth transistor T4 is coupled with the first clock signal CK1”; ¶ 0021: “A second end of the second transistor T2 is coupled with the first node N1”; Examiner: The first output node control circuit (T4) and the second output node control circuit (T2) are both gated by the same first clock signal CK1, so the first and second output control ends are a same output control end.]; or [Examiner: Limitations recited in the alternative (“or”) and thus only one of the alternative limitations needs to be taught to anticipate the claim.],
the first output control end (Tx1) and the second output control end (Tx2) are different output control ends [Examiner: Limitations recited in the alternative (“or”) and thus only one of the alternative limitations needs to be taught to anticipate the claim.].
Regarding claim 9:
Tseng discloses:
9. (Currently Amended) The driving circuit according to claim 2, further comprising a second on-off control circuit (172) [Tseng: Fig.2: seventh transistor T7; ¶ 0027: “the second capacitor C2 is coupled with the first node N1 via the seventh transistor T7”];
wherein the second output node (NO2) [Tseng: Fig.1: first node N1] is electrically connected to the control end of the second output circuit (12) [Tseng: Fig.1: sixth transistor T6; ¶ 0025: “A control end of the sixth transistor T6 is coupled with a first end of the second capacitor C2”] through the second on-off control circuit (172) [Tseng: Fig.2: seventh transistor T7; ¶ 0027: “a first end of the seventh transistor T7 is coupled with the first node N1, and a second end of the seventh transistor T7 is coupled with the first end of the second capacitor C2”];
the second on-off control circuit (172) [Tseng: Fig.2: seventh transistor T7] is configured to control the second output node (NO2) [Tseng: Fig.1: first node N1] to be electrically connected to the control end of the second output circuit (12) [Tseng: Fig.1: sixth transistor T6] in at least a part of a maintenance period comprised in a display period [Tseng: ¶ 0027: “A control end of the seventh transistor T7 is coupled with the second voltage VEE”; Examiner: With its gate held at VEE, the P-type T7 is maintained on and keeps N1 (NO2) connected to the C2 node (T6’s control end) throughout operation, including during the maintenance period (stages t3-t6 per the claim 17 construction); the limitation requires only connection during at least part of that period, not disconnection.]; or [Examiner: Limitations recited in the alternative (“or”) and thus only one of the alternative limitations needs to be taught to anticipate the claim.],
wherein the driving circuit further comprises a second output control circuit (42) [Examiner: Limitations recited in the alternative (“or”) and thus only one of the alternative limitations needs to be taught to anticipate the claim.],
wherein the second output control circuit (42) is electrically connected to each of the second output node (NO2), a third clock signal end (ECK), and a second input end (ESTV), and configured to control the second output node (NO2) to be electrically connected to the second input end (ESTV) under the control of a third clock signal provided by the third clock signal end (ECK) [Examiner: Limitations recited in the alternative (“or”) and thus only one of the alternative limitations needs to be taught to anticipate the claim.].
Regarding claim 17:
Tseng discloses:
17. (Currently Amended) A driving method applied to the driving circuit according to claim 1,
wherein a display period comprises a refreshing period and a maintenance period [Tseng: ¶ 0028: “he operating process of the shift register may include the following stages”; Examiner: The operation cycle reads on the display period; stages t1-2 read on the refreshing period and stages t3-t6 read on the maintenance period.];
the driving method comprises: in the refreshing period(13) [Tseng: Fig.1: fourth transistor T4], the first output node (NO1) [Tseng: Fig.1: second node N2] to be electrically disconnected from the second voltage end (V2) [Tseng: Fig.1: second voltage VEE] under the control of the first output control signal provided by the first output control end (Tx1) [Tseng: Fig.1: first clock signal CK1; ¶ 0029: “ the first clock signal CK1 and the second clock signal CK2 are high levels … the second transistor T2 and the fourth transistor T4 are turned off”; ¶ 0030: “The first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off”; Examiner: In stages t1-t2 (refreshing period), CK1 is high, T4 is off, and N2 (NO1) is disconnected from VEE (V2)];
in at least a part of the maintenance period, controlling, by the first output node control circuit (13) [Tseng: Fig.1: fourth transistor T4], the first output node (NO1) [Tseng: Fig.1: second node N2] to be electrically connected to the second voltage end (V2) [Tseng: Fig.1: second voltage VEE; ¶ 0031: “The second voltage VEE is input to the second node N2 via the fourth transistor T4”] under the control of the first output control signal provided by the first output control end (Tx1) [Tseng: Fig.1: first clock signal CK1], to cause the first output circuit (11) [Tseng: Fig.1: fifth transistor T5] to control the driving signal output end (GT) [Tseng: Fig.1: signal output end VOUT] to be electrically connected to the first voltage end (V1) [Tseng: Fig.1: first voltage VDD] under the control of the potential of the first output node (Tx1) [Tseng: Fig.1: first clock signal CK1; ¶ 0031: “the first clock signal CK1 is a low level. The second transistor T2 and the fourth transistor T4 are turned on”; Examiner: This occurs in stages t3-t6 (maintenance period)].
Regarding claim 18:
Tseng discloses:
18. (Original) The driving method according to claim 17,
wherein the driving circuit further comprises a second output node control circuit (21) [Tseng: Fig.1: second transistor T2];
the driving method comprises:
in the refreshing period [Tseng: ¶ 0028; Examiner: Stages t1-t2 per the claim 17 construction], controlling, by the second output node control circuit (21) [Tseng: Fig.1: second transistor T2], the second output node to be electrically disconnected from a third voltage end (V3) [Tseng: Fig.1: first voltage VDD] under the control of a second output control signal provided by a second output control end (Tx2) [Tseng: Fig.1: first clock signal CK1; ¶ 0029: “during charging stage t1, the first clock signal CK1 and the second clock signal CK2 are high levels … the second transistor T2 and the fourth transistor T4 are turned off”];
in at least a part of the maintenance period [Tseng: ¶ 0028; Examiner: Stages t3-t6 per the claim 17 construction], controlling, by the second output node control circuit (21) [Tseng: Fig.1: second transistor T2], the second output node (NO2) [Tseng: Fig.1: first node N1] to be electrically connected to the third voltage end (V3) [Tseng: Fig.1: first voltage VDD] under the control of the second output control signal provided by the second output control end (Tx2) [Tseng: Fig.1: first clock signal CK1; ¶ 0031: “during reset stage t3 … the first clock signal CK1 is a low level. The second transistor T2 and the fourth transistor T4 are turned on … The first voltage VDD is input to the first node N1 via the second transistor T2”], to cause the second output circuit (12) [Tseng: Fig.1: sixth transistor T6] to control the driving signal output end (GT) [Tseng: Fig.1: signal output end VOUT] to be electrically disconnected from the output signal end (S1) [Tseng: Fig.1: second clock signal CK2] under the control of the potential of the second output node (NO2) [Tseng: Fig.1: first node N1; ¶ 0031: “the third transistor T3 and the sixth transistor T6 are turned off at the same time.”; Examiner: With N1 (NO2) pulled to VDD, the P-type sixth transistor T6 is turned off, disconnecting VOUT (GT) from CK2 (the output signal end)].
Regarding claim 26:
Tseng discloses:
26. (Currently Amended) A driving module [Tseng: Fig.10: gate drive circuit; ¶ 0034: “ the present exemplary embodiment also provides a gate drive circuit, the gate drive circuit including any one of the above shift register units”], comprising
multiple stages of the driving circuits [Tseng: Fig.10: first to fourth shift register units SR1, SR2, SR3 and SR4; ¶ 0034: “ a plurality of shift register units, such as the first shift register unit SR1, the second shift register unit SR2, the third shift register unit SR3 and the fourth shift register unit SR4”] each according to claim 1 [Tseng: Figs.1 and 10: shift register units; Examiner: See claim 1 above.].
Regarding claim 29:
Tseng discloses:
29. (Original) A display device [Tseng: ¶ 0038: “Further, the present exemplary embodiment also provides a display panel, the display panel including any one of the above gate drive circuits”] comprising the driving module according to claim 26 [Tseng: Fig.10: gate drive circuit; ¶ 0034: “ the present exemplary embodiment also provides a gate drive circuit, the gate drive circuit including any one of the above shift register units”; Examiner: See claim 26 above.].
Allowable Subject Matter
Claims 6-8, 10, 13, 15, 19, 22, 25, and 27-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6:
The prior art does not teach or suggest either singularly or in combination the at least claimed “a second node control circuit (31) and an on-off control circuit (32), wherein the second node control circuit (31) is electrically connected to a second node (N2), and configured to control a potential of the second node (N2); the on-off control circuit (32) is electrically connected to each of a fourth voltage end (V4), the second node (N2), and the second output node (NO2), and configured to control the second node (N2) to be electrically connected to or electrically disconnected from the second output node (NO2) under the control of a fourth voltage signal provided by the fourth voltage end (V4)”, in combination with the other recited claim features.
Regarding claims 7, 10, 13:
Claims 7, 10, 13 depend on claim 6 and are found allowable for at least the same reason as discussed above.
Regarding claim 8:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the driving circuit further comprises a first on-off control circuit (32); the first output node (NO1) is electrically connected to the control end of the first output circuit (11) through the first on-off control circuit (32); the first on-off control circuit (32) is configured to control the first output node to be electrically connected to the control end of the first output circuit (11) in at least a part of a maintenance period comprised in a display period; or, wherein the driving circuit further comprises a first output control circuit (41), wherein the first output control circuit (41) is electrically connected to each of a first clock signal end, a fifth voltage end, the first output node, a second clock signal end, and the first voltage end (V1), and configured to control the first output node to be electrically connected to the fifth voltage end under the control of a first clock signal provided by the first clock signal end, and control the first output node to be electrically connected to the first voltage end (V1) under the control of a second clock signal provided by the second clock signal end”, in combination with the other recited claim features.
Regarding claim 15:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the first control circuit comprises a third node control circuit, a fourth node control circuit, and a first node control circuit; the third node control circuit is electrically connected to each of a third node, a third clock signal end, a fifth voltage end, and the second output node, and configured to control the third node to be electrically connected to the fifth voltage end under the control of a third clock signal provided by the third clock signal end, and write the third clock signal into the third node under the control of the potential of the second output node, and maintain a potential of the third node; the fourth node control circuit is electrically connected to each of the third node, a fourth clock signal end, and a fourth node, and configured to write a fourth clock signal provided by the fourth clock signal end into the fourth node under the control of the potential of the third node; the first node control circuit is electrically connected to each of the fourth clock signal end, the fourth node, the first output node, the second output node, and the first voltage end (V1), and configured to control the fourth node to be electrically connected to the first output node under the control of the fourth clock signal, and control the first output node to be electrically connected to the first voltage end (V1) under the control of the potential of the second output node”, in combination with the other recited claim features.
Regarding claim 19:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the driving circuit further comprises a first output control circuit (41); the first output control circuit (41) is electrically connected to a first clock signal end; the driving circuit further comprises a second node control circuit (31) and an on-off control circuit (32); the second node control circuit (31) is electrically connected to the first clock signal end, and the output signal end (S1) is a second clock signal end; a frequency of a first clock signal provided by the first clock signal end and a frequency of a second clock signal provided by the second clock signal end are equal to a frequency of a data voltage provided to a data line in the display period or, wherein the first output control end (Tx1) and the second output control end (Tx2) are different output ends; in the maintenance period, a first period is a period where the first output node is controlled by the first output node control circuit (13) to be electrically connected to the second voltage end (V2); a second period is a period where the second output node is controlled by the second output node control circuit (21) to be electrically connected to the third voltage end (V3); the first period is greater than the second period; or, wherein the first output control signal is a square wave signal, and the second output control signal is a square wave signal; a frequency of the first output control signal is greater than a display refreshing frequency, and a frequency of the second output control signal is greater than the display refreshing frequency”, in combination with the other recited claim features.
Regarding claim 22:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein in the refreshing period, the first output control signal is a first control voltage signal, and the second output control signal is a second control voltage signal; in the maintenance period, the first output control signal is a third control voltage signal, and the second output control signal is a fourth control voltage signal; the first control voltage signal is different from the third control voltage signal, and the second control voltage signal is different from the fourth control voltage signal; wherein the first control voltage signal, the second control voltage signal, the third control voltage signal, and the fourth control voltage signal are direct current voltage signals; or, wherein the first control voltage signal is a direct current voltage signal, and the second control voltage signal is a square wave voltage signal; the third control voltage signal is a direct current voltage signal, and the fourth control voltage signal is a square wave voltage signal”, in combination with the other recited claim features.
Regarding claim 25:
The prior art does not teach or suggest either singularly or in combination the at least claimed “further comprising: in the maintenance period, stopping providing a clock signal to each of clock signal ends, and stopping providing an input signal to each of input ends”, in combination with the other recited claim features.
Regarding claim 27:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the driving module comprises an odd-stage driving circuit and an even-stage driving circuit;
the driving circuit comprises the first output node control circuit (13) and a second output node control circuit (21); a display period comprises a maintenance period; the driving method comprises: in the maintenance period, stopping providing a clock signal and an input signal to the odd- stage driving circuit; in at least a part of the maintenance period, in the odd-stage driving circuit, controlling, by the first output node control circuit (13), the first output node to be electrically connected to the second voltage end (V2), to cause the first output circuit (11) to control the driving signal output end (GT) to be electrically connected to the first voltage end (V1); controlling, by the second output node control circuit (21), the second output node to be electrically connected to a third voltage end (V3), to cause the second output circuit (12) to control the driving signal output end (GT) to be electrically disconnected from the output signal end (S1) under the control of the potential of the second output node; in the maintenance period, providing the clock signal and the input signal normally to the even-stage driving circuit”, in combination with the other recited claim features.
Regarding claim 28:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the driving module comprises an odd-stage driving circuit and an even-stage driving circuit;
the driving circuit comprises the first output node control circuit (13) and a second output node control circuit (21); a display period comprises a maintenance period; the driving method comprises: in the maintenance period, stopping providing a clock signal and an input signal to the even-stage driving circuit; in at least a part of the maintenance period, in the even-stage driving circuit, controlling, by the first output node control circuit (13), the first output node to be electrically connected to the second voltage end (V2), to cause the first output circuit (11) to control the driving signal output end (GT) to be electrically connected to the first voltage end (V1); controlling, by the second output node control circuit (21), the second output node to be electrically connected to a third voltage end (V3), to cause the second output circuit (12) to control the driving signal output end (GT) to be electrically disconnected from the output signal end (S1) under the control of the potential of the second output node; in the maintenance period, providing the clock signal and the input signal normally to the odd-stage driving circuit”, in combination with the other recited claim features.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[Ryu; Jie Won et al., US 20240013693 A1] discloses:
“This disclosure is directed towards systems and methods of power saving in electronic displays based on changing clock signal frequencies supplied to the gate-in-panel (GIP) circuitry during extended blanking modes of the electronic display. The display driver circuitry of the display may reduce and/or halt clock signal frequencies sent to GIP circuitry in the display, to reduce power output during extended blanking modes of the electronic display,” as recited in the abstract.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Koosha Sharifi-Tafreshi whose telephone number is (571)270-5897. The examiner can normally be reached Mon - Fri 8AM to 5PM EST.
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/KOOSHA SHARIFI-TAFRESHI/Primary Examiner, Art Unit 2628
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