Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 3-4, 6-9, and 11-15 are amended. Claims 16-20 are newly added. Claims 1-20 are currently under review.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 29, 2025 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 8-9, 14-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Li (Pub. No.: US 2024/0155902 A1) in view of Zhang et al. (Pub. No.: CN113838421A) hereinafter referred to as Zhang, for purposes of examination please refer to Pub. No.: US 2024/0119897 A1.
With respect to Claim 1, Li teaches a pixel circuit (fig. 3, item 20; ¶69), having a first reset period and a data writing period (fig. 4, the data write stage P1 includes a first reset period (first and second dashed interval of P1) and a data writing period (third dashed interval of P1), the first reset period preceding the data writing period (fig. 4), comprising: a driving sub-circuit (fig. 3, item T3; ¶71) connected to a first node (fig. 3, item N1), a second node (fig. 3, item N2) and a third node (fig. 3, item N3), wherein the driving sub-circuit is configured to control a circuit between the second node and the third node to be turned on or off under control of a voltage of the first node (¶63); a data writing sub-circuit (fig. 3, item T2; ¶71) connected to a first scan signal terminal (fig. 3, item SP*; ¶65), a data signal terminal (fig. 3, item DL) and the second node (fig. 3, item N2), wherein the data writing sub-circuit is configured to, in the data writing period (fig. 3, third dashed interval in P1, item VSP* is low), transmit a data signal received at the data signal terminal to the second node in response to a first scan signal received at the first scan signal terminal (¶65; ¶67); a first reset sub-circuit (fig. 3, item T5 comprising items T51 and T52; ¶65) connected to a first initialization signal terminal (fig. 3, terminal receiving item VREF2), a first reset signal terminal and the first node (fig. 3, a first reset signal terminal and the first node is the same location = N1), wherein the first reset sub-circuit is configured to, in the first reset period, transmit a first initialization signal received at the first initialization signal terminal to the first node in response to a first reset signal received at the first reset signal terminal (fig. 3, fig. 4, occurs within the first and second dashed interval of P1); and a second reset sub-circuit (fig. 3, item T8) connected to a second initialization signal terminal (fig. 3, terminal receiving item DVH), a second reset signal terminal and the second node (a second reset signal terminal and the second node is the same location = N2), wherein the second reset sub-circuit (fig. 3, item T8) is configured to, in the first reset period (fig. 4, first dashed interval of P1), transmit a second initialization signal (fig. 3, item DVH) received at the second initialization signal terminal to the second node (fig. 3, item N2) in response to a second reset signal (fig. 3, item SP) received at the second reset signal terminal (fig. 3, control terminal of item T8).
Li does not mention and in the first reset period, a voltage of the second initialization signal is greater than a voltage of the first initialization signal.
Zhang teaches a pixel circuit (fig. 5B; ¶89), having a first reset period (fig. 5C, first reset period = t1 and t2) and a data writing period (fig. 5C, data writing period = t3 and t4), the first reset period preceding the data writing period (fig. 5C), comprising: a driving sub-circuit (fig. 5B, item T1) connected to a first node (fig. 5B, item N1), a second node (fig. 5B, item N3) and a third node (fig. 5B, item N2), wherein the driving sub-circuit (fig. 5B, item T1) is configured to control a circuit between the second node and the third node to be turned on or off under control of a voltage of the first node (fig. 5B; ¶118); a data writing sub-circuit (fig. 5B, item T2) connected to a first scan signal terminal (fig. 5B, first scan signal terminal is connected to the control terminal of T2), a data signal terminal (fig. 5B, data signal terminal is connected to Vdata) and the second node (fig. 5B, item N3); a first reset sub-circuit (fig. 5B, item T3) connected to a first initialization signal terminal (fig. 5B, first initialization signal terminal is connected to Vinit1), a first reset signal terminal and the first node (fig. 5B, item N1), wherein the first reset sub-circuit is configured to, in the first reset period, transmit a first initialization signal received at the first initialization signal terminal to the first node in response to a first reset signal received at the first reset signal terminal (¶115); and a second reset sub-circuit (fig. 5B, item T6) connected to a second initialization signal terminal (fig. 5B, second initialization signal terminal is connected to Vhold), a second reset signal terminal and the second node (fig. 5B, item N3), wherein the second reset sub-circuit is configured to, in the first reset period, transmit a second initialization signal received at the second initialization signal terminal to the second node in response to a second reset signal received at the second reset signal terminal (fig. 5C; ¶140-141); and in the first reset period (fig. 5C, first reset period = t1 and t2), a voltage of the second initialization signal is greater than a voltage of the first initialization signal (¶109, “Vinit1 is a low voltage (for example, it can be a grounded voltage or other low voltages)”; ¶141, “Vhold, which can be higher than VDD. At this time, the voltage difference Vgd between the gate electrode and the drain electrode of the first transistor T1 is equal to the difference value between Vinit1 and Vhold and is smaller than Vth (for example, it can be smaller than OV), so the first transistor T1 is either in a turn-off state or in a saturated state, which is beneficial to stabilizing the characteristics of the first transistor T1”).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the pixel circuit of Li, such that in the first reset period, a voltage of the second initialization signal is greater than a voltage of the first initialization signal, as taught by Zhang so as to stabilize the characteristics of od the driving sub-circuit (¶141).
With respect to Claim 3, claim 1 is incorporated, Li teaches wherein the pixel circuit further has a second reset period (fig. 4, fourth dashed interval of data write stage P1) and a first light-emitting period (fig. 4, first high duration of VEMIT of the interval of light emission retention stage P2), the second reset period intervening between the data writing period and the first light-emitting period (fig. 4); the second reset sub-circuit (fig. 3, item T8) is further configured to, in the second reset period, transmit the second initialization signal received at the second initialization signal terminal to the second node in response to the second reset signal received at the second reset signal terminal (¶57).
With respect to Claim 8, claim 1 is incorporated, Li teaches further comprising: a plurality of third transistors (fig. 3, items T41 and T42 = T4; ¶81) connected in series, wherein control electrodes of the third transistors are connected to the second scan signal terminal (fig. 3, item S2: second scan signal; ¶82); among two third transistors located on two ends of the plurality of third transistors connected in series, a second electrode of one third transistor is connected to the first node (fig. 3; ¶65, “A first electrode of the compensation transistor T4 is electrically connected to the first node N1”), and a first electrode of another third transistor is connected to the third node (fig. 3; ¶65, “a second electrode of the compensation transistor T4 is electrically connected to the third node N3”); the second reset sub-circuit includes a second transistor (fig. 3, item T8); the second transistor and the third transistors are P-type transistors (¶70, “all the thin-film transistors in the pixel driving circuit 20 are of the same channel type, for example, p-type transistors”); and a non-operating voltage of the second scan signal (fig. 4, item VS1 is low when it is a non-operating voltage) received at the second scan signal terminal is less than a non-operating voltage of the second reset signal (fig. 4, item VSP is high when it is a non-operating voltage) received at the second reset signal terminal.
With respect to Claim 9, claim 1 is incorporated, Li teaches a plurality of pixel circuits according to claim 1, wherein the plurality of pixel circuits are arranged in M rows and N columns (fig. 1, M=3, N=4); each row includes N pixel circuits arranged in a first direction (fig. 1); each column includes M pixel circuits arranged in a second direction (fig. 1); M > 1, N> 1, and M and N are integers (fig. 1; ¶52).
With respect to Claim 14, claim 9 is incorporated, Li teaches a display apparatus (¶279), comprising: the display panel (fig. 1; ¶52) according to claim 9.
With respect to Claim 15, claim 1 is incorporated, Li teaches a driving method of a pixel circuit (fig. 4), used for driving the pixel circuit (fig. 3) according to claim 1, the method comprising the first reset period (fig. 4, first and second dashed interval of the data write stage P1) and the data writing period (fig. 4, third dashed interval of the data write stage P1), wherein the first reset period precedes the data writing period (fig. 4); the first reset period includes a first sub-period (fig. 4, second dashed interval of the data write stage P1) and a second sub-period (fig. 4, first dashed interval of the data write stage P1), wherein the first sub-period follows the second sub-period (fig. 4); in the first sub-period (fig. 4, second dashed interval of the data write stage P1), the first reset sub-circuit (fig. 3, item T5) transmits the first initialization signal (fig. 3, item VREF2) received at the first initialization signal terminal to the first node (fig. 3, item N1) in response to the first reset signal (fig. 3, item S1) received at the first reset signal terminal; and in the second sub-period (fig. 4, first dashed interval of the data write stage P1), the second reset sub-circuit (fig. 3, item T8) transmits the second initialization signal (fig. 3, item DVH) received at the second initialization signal terminal to the second node (fig. 3, item N2) in response to the second reset signal (fig. 3, item SP) received at the second reset signal terminal (¶57).
With respect to Claim 16, claim 1 is incorporated, Li teaches wherein the first reset sub-circuit (fig. 3,item T5) includes a plurality of first transistors (fig. 3, items T51 and T52) connected in series; control electrodes of the first transistors are connected to the first reset signal terminal (fig. 3, connected to item S1); among two first transistors located on two ends of the plurality of first transistors connected in series, a first electrode of one first transistor is connected to the first initialization signal terminal (fig. 3, connected to item VREF2), and a second electrode of another first transistor is connected to the first node (fig. 3, item N1); the second reset sub-circuit (fig. 3, item T8) includes a second transistor; the first transistors and the second transistor are P-type transistors (¶70, all the thin-film transistors in the pixel driving circuit 20 are of the same channel type, for example, p-type transistors “”); a non-operating voltage of the first reset signal (fig. 4, item VS1 is low when it is a non-operating voltage) is less than a non-operating voltage of the second reset signal (fig. 4, item VSP is high when it is a non-operating voltage).
With respect to Claim 18, claim 15 is incorporated, Li further comprising: a second reset period (fig. 4, fourth dashed interval of the data write stage P1) and a first light-emitting period (fig. 4, first VEMIT high in the light emission retention stage P2), the second reset period intervening between the data writing period and the first light-emitting period (fig. 4), wherein in the second reset period, the second reset sub-circuit (fig. 3, item T8) transmits the second initialization signal (fig. 3, item DVH) received at the second initialization signal terminal to the second node (fig. 3, item N2) in response to the second reset signal received at the second reset signal terminal (¶57, “After a data voltage is written to the drive transistor T3, a voltage of the first electrode p31 of the drive transistor T3 is leaked, and the leakage is more obvious in the case of low-frequency driving, causing a relatively large drift of the potential of the first electrode p31 of the drive transistor T3. In this case, the bias transistor T8 is controlled to be turned on, and the bias voltage is written to the first electrode p31 of the drive transistor T3 through the bias transistor T8 so that a bias state of the drive transistor T3 can remain consistent with a bias state when the data voltage is written”).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Li and Zhang as applied to claim 9 above, and further in view of Yonebayashi (Pub. No.: US 2024/0233633 A1).
With respect to Claim 13, Li teaches wherein in the second direction, from a first row of pixel circuits to a last row of pixel circuits (fig. 1), M rows of pixel circuits are a 1st row of pixel circuits to an M-th row of pixel circuits (fig. 1).
Li and Zhang combined do not mention the display panel further comprises: a fifth gate driver circuit including M fifth shift registers in cascade, wherein from a first stage fifth shift register to a last-stage fifth shift register, the M fifth shift registers are a 1st fifth shift register to an M-th fifth shift register; a fifth shift register includes a fifth signal output terminal; first scan signal terminals of a P-th row of pixel circuits are connected to a fifth signal output terminal of a P-th fifth shift register; P ≤ M, and P is an integer.
Yonebayashi teaches a display panel (fig. 1, item 11; ¶128), comprising: a plurality of pixel circuits (fig. 1, item 15; ¶129), a pixel circuit comprises: a driving sub-circuit (fig. 3, item T4; ¶141) connected to a first node (fig. 3, item N2); a data writing sub-circuit (fig. 3, item T3; ¶141) connected to a first scan signal terminal (fig. 3, item PS: first scan signal), a first reset sub-circuit (fig. 3, item T1; ¶141) connected to a first initialization signal terminal (fig. 3, item Vini = first initialization signal), wherein the plurality of pixel circuits are arranged in M rows and N columns (fig. 1); each row includes N pixel circuits arranged in a first direction; each column includes M pixel circuits arranged in a second direction (fig. 1); M > 1, N> 1, and M and N are integers; the display panel further comprises: a fifth gate driver circuit (fig. 7, item 301; ¶165) including M fifth shift registers in cascade (fig. 7), wherein from a first stage fifth shift register to a last-stage fifth shift register, the M fifth shift registers are a 1st fifth shift register to an M-th fifth shift register (fig. 7); a fifth shift register includes a fifth signal output terminal; first scan signal terminals of a P-th row of pixel circuits are connected to a fifth signal output terminal of a P-th fifth shift register (fig. 7, item OUT1); P ≤ M, and P is an integer (fig. 7).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display panel of Li and Zhang, such that the display panel further comprises: a fifth gate driver circuit including M fifth shift registers in cascade, wherein from a first stage fifth shift register to a last-stage fifth shift register, the M fifth shift registers are a 1st fifth shift register to an M-th fifth shift register; a fifth shift register includes a fifth signal output terminal; first scan signal terminals of a P-th row of pixel circuits are connected to a fifth signal output terminal of a P-th fifth shift register; P ≤ M, and P is an integer, as taught by Yonebayashi so as to provide a means to perform the initialization operation, data write operation with threshold compensation, and light emitting operation (¶188).
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Li and Zhang as applied to claims 1and 15 above, and further in view of Park et al. (Pub. No.: US 2021/0027702 A1) hereinafter referred to as Park.
With respect to Claim 17, claim 1 is incorporated, Li teaches wherein the pixel circuit further has a light-emitting period (fig. 4, light emitting period = light emission retention stage P2); and the pixel circuit further comprises: a first light-emitting control sub-circuit (fig. 3, item T1) connected to the second node (fig. 3, item N2: second node), a first power signal terminal (fig. 3, first power signal = PVDD) and a first enable signal terminal (fig. 3, control terminal of item T1 connected to EMIT = first enable signal terminal), wherein the first light-emitting control sub-circuit is configured to, in the light-emitting period, transmit a first power signal received at the first power signal terminal to the second node in response to a first enable signal received at the first enable signal terminal (¶65; ¶67); and a second light-emitting control sub-circuit (fig. 3, item T6) connected to the third node (fig. 3, item N3: third node), a fourth node (fig. 3, item N4: fourth node) and a second enable signal terminal (fig. 3, control terminal of item T6 = second enable signal terminal), wherein the second light-emitting control sub-circuit is configured to, in the light-emitting period, transmit a voltage of the third node to the fourth node in response to a second enable signal received at the second enable signal terminal (¶67); the fourth node is configured to be connected to an anode of a light-emitting device (fig. 3).
Li and Zhang combined do not teach wherein in the light-emitting period, a start time of an operating voltage of the first enable signal precedes a start time of an operating voltage of the second enable signal.
Park teaches a pixel circuit (fig. 2A) comprising: a driving sub-circuit (fig. 2A, item T1) connected to a first node (fig. 2A, item N1); a data writing sub-circuit (fig. 2A, item T2) connected to a first scan signal terminal (fig. 2A, item SLn: first scan signal); a first reset sub-circuit (fig. 2A, item T7) connected to a first initialization signal terminal (fig. 2A, item Vinit: first initialization signal); wherein the pixel circuit further has a light-emitting period (fig. 3, item P9; ¶118); and the pixel circuit further comprises: a first light-emitting control sub-circuit (fig. 2A, item T6); a second light-emitting control sub-circuit (fig. 2A, item T5); wherein in the light-emitting period, a start time of an operating voltage of the first enable signal precedes a start time of an operating voltage of the second enable signal (fig. 3; ¶118).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined pixel circuit of Li and Zhang, wherein in the light-emitting period, a start time of an operating voltage of the first enable signal precedes a start time of an operating voltage of the second enable signal, as taught by Park to provide alternative means for light emission.
With respect to Claim 20, Li teaches wherein the pixel circuit further includes a first light-emitting control sub-circuit (fig. 3, item T1) and a second light-emitting control sub-circuit (fig. 3, item T6); the method further comprises: a light-emitting period (fig. 4, light emitting period = light emission retention period P2); in the light-emitting period, the first light-emitting control sub-circuit transmits a first power signal received at a first power signal terminal to the second node in response to a first enable signal received at a first enable signal terminal (¶65; ¶67), and the second light-emitting control sub-circuit transmits a voltage of the third node to a fourth node in response to a second enable signal received at a second enable signal terminal (¶67).
Li and Zhang combined do not teach and a start time of an operating voltage of the first enable signal precedes a start time of an operating voltage of the second enable signal.
Park teaches a pixel circuit (fig. 2A) comprising: a driving sub-circuit (fig. 2A, item T1) connected to a first node (fig. 2A, item N1); a data writing sub-circuit (fig. 2A, item T2) connected to a first scan signal terminal (fig. 2A, item SLn: first scan signal); a first reset sub-circuit (fig. 2A, item T7) connected to a first initialization signal terminal (fig. 2A, item Vinit: first initialization signal); wherein the pixel circuit further has a light-emitting period (fig. 3, item P9; ¶118); and the pixel circuit further comprises: a first light-emitting control sub-circuit (fig. 2A, item T6); a second light-emitting control sub-circuit (fig. 2A, item T5); wherein in the light-emitting period, a start time of an operating voltage of the first enable signal precedes a start time of an operating voltage of the second enable signal (fig. 3; ¶118).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined driving method of Li and Zhang, wherein in the light-emitting period, a start time of an operating voltage of the first enable signal precedes a start time of an operating voltage of the second enable signal, as taught by Park to provide alternative means for light emission.
Allowable Subject Matter
Claims 2, 4-8, 10-12, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to Claim 2, Although Sung et al. (Pub. No.: US 2013/0128015 A1) hereinafter referred to as Sung, teaches in paragraph 158 and figure 5 that a voltage at the source of transistor ETR subtracted from the gate voltage is 9V, none of the prior art teaches “wherein in the first reset period, an absolute value of a difference between the voltage of the second initialization signal and the voltage of the first initialization signal is in a range of 10 V to 13 V, inclusive” including all the base limitations. With respect to Claim 4, Lee et al. (Pub. No.: US 2023/0410741 A1) hereinafter referred to as Lee, teaches in figure 4A a frame driven at a first refresh rate= 240Hz and in figure 4B a frame driven at a second refresh rate= 120Hz, at the second refresh rate, one frame further includes at least one holding cycle; the at least one holding cycle follows the refresh cycle (¶101 and ¶103). None of the prior art teaches “the holding cycle includes at least one third reset period and a second light-emitting period; the at least one third reset period precedes the second light-emitting period; the pixel circuit further comprises: a first storage sub-circuit connected to a first voltage signal terminal and the fourth node, wherein the first storage sub-circuit is configured to, in the first reset period and the third reset period, pull up or pull down a voltage of the fourth node in response to a first voltage signal received at the first voltage signal terminal; wherein a voltage of one of the third reset signal and the first voltage signal in the refresh cycle is greater than the voltage of one of the third reset signal and the first voltage signal in the holding cycle; and a voltage of another of the third reset signal and the first voltage signal in the holding cycle is greater than the voltage of another of the third reset signal and the first voltage signal in the refresh cycle” including all the base limitations. With respect to Claim 10, Li teaches wherein the pixel circuit includes a compensation sub-circuit (fig. 3, item T4 = T41 and T42; ¶65; ¶81); in the second direction, from a first row of pixel circuits to a last row of pixel circuits, M rows of pixel circuits are a 1st row of pixel circuits to an M-th row of pixel circuits (fig. 1; ¶52). Yonebayashi (Pub. No.: US 2024/0233633 A1) teaches a gate driver 301 in figure 18 including (M + Q) first shift registers in cascade, wherein from a first-stage first shift register to a last-stage first shift register, the (M + Q) first shift registers are a 1st first shift register to an (M + Q)-th first shift register; wherein a first shift register includes a first signal output terminal; first reset signal terminals of a P-th row of pixel circuits are connected to a first signal output terminal of a P-th first shift register, however none of the prior art teaches the display panel further comprises a first gate driver including (M + Q) first shift registers in cascade, such that “second scan signal terminals of the P-th row of pixel circuits are connected to a first signal output terminal of a (P + Q)-th first shift register; P ≤ M, Q > 0, and P and Q are integers” including all the base limitations. With respect to Claim 11, Li teaches a third reset sub-circuit (fig. 3, item T7); in the second direction, from a first row of pixel circuits to a last row of pixel circuits, M rows of pixel circuits are a 1st row of pixel circuits to an M-th row of pixel circuits (fig. 1). Yonebayashi (Pub. No.: US 2024/0233633 A1) teaches a gate driver 301 in figure 18 including (M + Q) first shift registers in cascade. None of the prior art teaches “second reset signal terminals and third reset signal terminals of a P-th row of pixel circuits are connected to a second signal output terminal of a P-th second shift register; P≤M, and P is an integer” including all the base limitations. With respect to Claim 12, Li teaches a first light-emitting control sub-circuit (fig. 3, item T1) and a second light-emitting control sub-circuit (fig. 3, item T6); in the second direction, from a first row of pixel circuits to a last row of pixel circuits, M rows of pixel circuits are a 1st row of pixel circuits to an M-th row of pixel circuits (fig. 1). Yonebayashi (Pub. No.: US 2024/0233633 A1) teaches a gate driver 301 in figure 18 including (M + Q) first shift registers in cascade. None of the prior art teaches “first enable signal terminals of a P-th row of pixel circuits are connected to a third signal output terminal of a P-th third shift register; P≤M, and P is an integer; and a fourth gate driver circuit including M fourth shift registers in cascade, wherein from a first-stage fourth shift register to a last-stage fourth shift register, and the M fourth shift registers are a 1st fourth shift register to an M-th fourth shift register; a fourth shift register includes a fourth signal output terminal; second enable signal terminals of the P-th row of pixel circuits are connected to a fourth signal output terminal of a P-th fourth shift register; P ≤ M, and P is an integer” including all the base limitations. With respect to Claim 19, Li teaches wherein the pixel circuit further includes a third reset sub-circuit (fig. 3, item T7), the third reset sub-circuit transmits a third initialization signal (fig. 3, item VREF1) received at a third initialization signal terminal to a fourth node (fig. 3, item N4) in response to a third reset signal (fig. 3, item SP) received at a third reset signal terminal. None of the prior art teaches “a first storage sub-circuit ; the method further comprises a third reset period; in the first reset period and the third reset period, and the first storage sub-circuit pulls up or pulls down a voltage of the fourth node in response to a first voltage signal received at a first voltage signal terminal” including all the base limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sung et al. (Pub. No.: US 2013/0128015 A1) hereinafter referred to as Sung see figure 5 and paragraph 158.
Lee et al. (Pub. No.: US 2023/0410741 A1) hereinafter referred to as Lee See figure 4A and 4B and paragraphs 101 and 103.
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/DONNA V Bocar/ Primary Examiner, Art Unit 2621
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