DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendment
The amendments to Claims 1-5 in the submission filed 11/27/2024 are acknowledged and accepted.
Pending Claims are 1-5.
Drawings
The drawings with 11 Sheets of Figs. 1-12 received on 11/27/2024 are acknowledged and accepted.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2,4-5, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nosaka et al (US 8,687,968 B2).
Regarding Claim 1, Nosaka teaches (fig 24) an optical computing apparatus (optical transreceiver, col 22, line 40-46 including laser 10, Mach-Zehnder modulators 11 and 15, col 22), comprising:
a plurality of stages including one or a plurality of Mach-Zehnder interference-type optical switches (Mach-Zehnder modulators 11,15, col 22, lines 47-52), wherein incident light is received as input in one of the plurality of stages (stage with Mach-Zehnder modulator 15, col 22, lines 47-52) that serves as an incident stage for receiving the incident light as input (light from laser 10, col 22), a phase of the incident light changed in advance (“The clock input from the serializer 12 to the NRZ-RZ conversion circuit 14 is adjusted to an optimum phase by the vector sum phase shifter 16”, col 23, lines 4-6), outside the optical computing apparatus, by a predetermined phase amount in accordance with a position in the incident stage where the incident light arrives (“Note that the optimum phase means the most appropriate phase relation between the NRZ signal light and the clock input to the Mach-Zehnder modulator 15.”, col 23), and
wherein the input light propagates in the optical computing apparatus in accordance with a control electric signal (control voltage VC) provided from outside the optical computing apparatus (“Adjusting the clock to the optimum phase is done by causing the phase control circuit 17 to, for example, monitor the waveform output from the vector sum phase shifter 16 and control it. The shift of the clock phase from the optimum phase is detected as, for example, voltage information. The phase control circuit 17 outputs a control voltage VC based on the information to adjust the clock to the optimum phase, thereby controlling the vector sum phase shifter 16”, col 23, lines 18-25).
Regarding Claim 2, Nosaka teaches (fig 24) the optical computing apparatus according to claim 1,
wherein the phase of the incident light is changed in advance, outside the optical computing apparatus (outside of Mach-Zehnder Modulators 11, 15), such that a phase difference between the incident light (light from laser 10) and output light exiting the optical computing apparatus is substantially 0 (“NRZ-RZ conversion circuit 14, col 22, lines 50-52, Non-Return to Zero to Return to zero conversion circuit, this indicates phase difference is zero between input and output light).
Regarding Claim 4, Nosaka teaches (fig 24) the optical computing apparatus according to claim 1,
further comprising a phase adjustment unit (“Adjusting the clock to the optimum phase is done by causing the phase control circuit 17 to, for example, monitor the waveform output from the vector sum phase shifter 16 and control it, col 23) configured to change the phase of the incident light, in the optical computing apparatus, by the predetermined phase amount.
Regarding Claim 5, Nosaka teaches (fig 24) an optical computing method executed by an optical computing apparatus (optical transreceiver, col 22, line 40-46 including laser 10, Mach-Zehnder modulators 11 and 15, col 22) including
a plurality of stages including one or a plurality of Mach-Zehnder interference-type optical switches (Mach-Zehnder modulators 11,15, col 22, lines 47-52), the method comprising:
receiving incident light as input in one of the plurality of stages (stage with Mach-Zehnder modulator 15, col 22, lines 47-52) that serves as an incident stage for receiving the incident light as input (light from laser 10, col 22), a phase of the incident light changed in advance (“The clock input from the serializer 12 to the NRZ-RZ conversion circuit 14 is adjusted to an optimum phase by the vector sum phase shifter 16”, col 23, lines 4-6), outside the optical computing apparatus, by a predetermined phase amount in accordance with a position in the incident stage where the incident light arrives (“Note that the optimum phase means the most appropriate phase relation between the NRZ signal light and the clock input to the Mach-Zehnder modulator 15.”, col 23), and
causing the input light to propagate in the optical computing apparatus in accordance with a control electric signal (control voltage VC) provided from outside the optical computing apparatus (“Adjusting the clock to the optimum phase is done by causing the phase control circuit 17 to, for example, monitor the waveform output from the vector sum phase shifter 16 and control it. The shift of the clock phase from the optimum phase is detected as, for example, voltage information. The phase control circuit 17 outputs a control voltage VC based on the information to adjust the clock to the optimum phase, thereby controlling the vector sum phase shifter 16”, col 23, lines 18-25).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nosaka et al (US 8,687,968 B2) and further in view of Avaya et al (JP 2018-036455 A, of record).
Regarding Claim 3, Nosaka teaches (fig 24) the optical computing apparatus according to claim 1.
However, Nosaka does not teach
wherein the plurality of stages correspond to a plurality of bits of the control electric signal, and wherein the plurality of stages are connected with each other such that a part of the incident light is selected, from among a plurality of parts of the incident light received in the incident stage, in accordance with the control electric signal, and output as output light.
Nosaka and Avaya are related as optical computing apparatus with plurality of stages.
Avaya teaches (fig 38A, B)
wherein the plurality of stages (two phase modulators b102, b103, para 122) correspond to a plurality of bits of the control electric signal (When the electric signals Xi and Yi are “1”, para 122), and wherein the plurality of stages (two phase modulators b102, b103, para 122) are connected with each other (as in fig 38) such that a part of the incident light is selected, from among a plurality of parts of the incident light received in the incident stage, in accordance with the control electric signal (signal provided by phase shifter b104, para 123), and output as output light (para 122, 123, as in fig 38).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the plurality of stages of Nosaka to include the plurality of bits of Avaya for the purpose of utilizing an optical logic circuit which speeds up computation (para 1 and Abstract).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al (US 11815780 B2) teaches (fig 4) an integrated Mac-Zehnder Interferometer with a phase shifter and plurality of stages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYOTSNA V DABBI whose telephone number is (571)270-3270. The examiner can normally be reached M-Fri: 9:00am-5:00pm.
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/JYOTSNA V DABBI/Primary Examiner, Art Unit 2872 9/5/2026
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