DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS’s) comply with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1, 27, 33, 44 – 45 objected to because of the following informalities:
Regarding claims 27, 33 and 45, the claims state that the digital/analog converter comprises an Analog-to-digital converter ADC or Digital-to-analog converter DAC; however, the ADC and DAC are separate units as evidenced by Applicant’s Fig. 15. Also, the Examiner has seen the term digital-to-analog converter written as digital/analog converter, which is contrary to how Applicant is using the term because Applicant is using said term to refer to both ADC and DAC, which may cause confusion. The Examiner suggests replacing first term “digital/analog converter” with “analog-to-digital converter (ADC) converter or Digital-to-analog converter DAC to …” in the independent claims and all other “digital/analog converter” terms with “ADC” or “DAC”, depending on context of the limitation, and remove language “comprises an Analog-to-Digital converter ADC” and “comprises a Digital-to-Analog converter DAC” as said language is redundant.
Also, with regards to claim 33, please amend as follows: “Digital-to-Analog converter (DAC) to convert the digital Tx signal into an analog baseband (BB) Tx signal,”, because a mixer down-converts (or upconverts) and a low pass filter passes the difference (baseband) frequency (or a high-pass filter to pass the sum (carrier) frequency). Looking at Fig. 15, the DAC is receiving a baseband signal. The mixers (“X” encircled) upconvert the baseband signal onto a carrier for transmission (high pass filter not shown). The original language appears to suggest that the DAC is downconverting the signal – not correct. The filters used for down-conversion and up-conversion are downstream the mixers such as the LPF shown on the receive side of Fig. 15. The LPF’s on the transmit side (upstream the mixers) are not relevant for down/up conversion but are used for different purpose.
Regarding claims 1 and 44, the language “wherein an RF chain comprises a digital/analog converter to convert between an analog signal and a digital signal” is borderline an antecedent issue, but the Examiner decided against 112-b because the reader can discern which branch by looking at Fig. 15. The Examiner recommends: “wherein at least one of the RF chains comprises a digital/analog converter to convert between an analog signal and a digital signal.” And, if Applicant accepts the Examiner’s position regarding the digital/analog converter, the suggested language would then read “wherein at least one of the RF chains comprises at least one of a digital-to-analog converter (ADC) or analog-to-digital converter (DAC) to convert between an analog signal and a digital signal.”
All dependent claims 27 – 43 and 45 are objected to for being dependent on an objected base claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 26 – 28, 33 – 39 and 43 – 45 are rejected under 35 U.S.C. 102(a)(a) as being anticipated by Cohen (US 20190293755 A1).
As to claims 26 and 44, Cohen discloses a vehicle comprising:
a system controller configured to control one or more vehicular systems of the vehicle based on radar-based information (Para. 30 Fig. 2 ECU 205); and
a radar system configured to generate the radar-based information, the radar system comprising:
a radar processor (Fig. 2 Digital Processor 115);
a Radio Head (RH) comprising:
a communication interface configured to communicate with a radar processor via a communication interconnect (Para.27 “In some examples in which the digital processor chip 115 is implemented as a hardware circuit included in a single package implementation, such as an SoC implementation, the receiver serial ports 160 are replaced with one or more digital data interfaces structured to communicate data bits in parallel, such as one or more busses, groups of communication lines, etc., that communicate with (e.g., electrically couple to) the hardware circuit implementing the receiver chip(s) 110 to thereby obtain the baseband received radar data from the receiver chip(s) 110. However, one or more serial data interfaces such as or similar to the receiver serial ports 160 may additionally or alternatively be used by the digital processor chip 115 in some example single package (e.g., SoC) implementations to obtain the baseband received radar data from the receiver chip(s) 110.” Here, the cited bus is mapped to the claimed communication interface.),
wherein the communication interface is configured to receive analog synchronization information from the radar processor (Fig. 7 shows communication timing circuitry 120 receiving system clock from the Digital Processor 700.),
and to communicate digital radar information with the radar processor (Fig. 7 port 7 and ADC’s 540, 545);
and one or more Radio Frequency (RF) chains to communicate radar RF signals corresponding to the digital radar information via one or more antennas (Fig. 7 item 105),
the one or more RF chains configured to process the radar RF signals based on the analog synchronization information (Fig. 7 timing circuitry 120 and clock port 135),
wherein an RF chain comprises a digital/analog converter to convert between an analog signal and a digital signal (Fig. 7 ADC’s 540, 545),
wherein the analog signal corresponds to a radar RF signal communicated by the RF chain via an antenna, wherein the digital signal corresponds to the digital radar information (Figure 7 item 110).
As to claim 27, Cohen discloses the apparatus of claim 26, wherein the one or more RF chains comprise a Receive (Rx) chain to receive a radar Rx signal and to generate an Rx Baseband (BB) signal by processing the radar Rx signal based on the analog synchronization information (Fig. 7 shows mixers feeding LPF’s wherein mixers are fed a clock signal via port 150),
wherein the digital/analog converter comprises an Analog-to-Digital (ADC) converter to convert the Rx BB signal into a digital Rx signal, wherein the communication interface is configured to transmit to the radar processor digital radar Rx information based on the digital Rx signal (Fig. 7 ADC’s 540, 455 and port 12 via the bus as cited in Para. 27 in claim 1).
As to claim 28, Cohen discloses the apparatus of claim 27, wherein the Rx chain comprises a Low Noise Amplifier (LNA) to provide an amplified Rx signal based on the radar Rx signal, and a frequency downconverter to provide a downconverted Rx signal by downconverting the amplified Rx signal based on the analog synchronization information, wherein the Rx BB signal is based on the downconverted Rx signal (Fig. 7 shows the mixers and LPF for down-conversion and shows LNA and port 150 for clock input via a bus as cited in Para. 27.).
As to claim 33, Cohen discloses the apparatus of claim 26, wherein the communication interface is configured to receive from the radar processor digital radar Tx information to define a digital Tx signal, wherein the digital/analog converter comprises a Digital-to-Analog Converter (DAC) to convert the digital Tx signal into a Tx Baseband (BB) signal (Fig. 7 DAC’s 420, 425), wherein the one or more RF chains comprise a Transmit (Tx) chain to transmit a radar Tx signal by processing the Tx B B signal based on the analog synchronization information (Figure 7 clock input port 135 and antennae ANT).
As to claim 34, Cohen discloses the apparatus of claim 33, wherein the Tx chain comprises a Low-Pass-Filter (LPF) to provide a filtered Tx signal based on the Tx BB signal, and a frequency upconverter to provide an upconverted Tx signal by upconverting the filtered Tx signal based on the analog synchronization information, wherein the radar Tx signal is based on the upconverted Tx signal (Fig. 7 port 135, LPF and IQ Mixers).
As to claim 35, Cohen discloses the apparatus of claim 33, wherein the digital radar Tx information comprises a sequence of digital radar Tx samples of the digital Tx signal (Para. 35 bits Fig. 7 SerDes).
As to claim 36, Cohen discloses the apparatus of claim 35comprising a memory to store the sequence of digital radar Tx samples (Fig. 7 item 105 RAM), wherein the RH is configured to transmit a plurality of repetitions of a radar Tx transmission (Fig. 7 ANT), the radar Tx transmission based on the sequence of digital radar Tx samples (Para. 59 TCXO 605 clock frequency and port 135 and mixer in combination with output of DAC’s provide for repetition frequency.).
As to claim 37, Cohen discloses the apparatus of claim 35, wherein the RH is configured to stream the sequence of digital radar Tx samples as an input to the DAC of the Tx chain (Fig. 7 DAC’s and Para. 28 “stream port 165” and item 105 “Data stream”).
As to claim 38, Cohen discloses the apparatus of claim 33, wherein the digital radar Tx information comprises waveform information to define a radar Tx waveform, wherein the RH is configured to generate the digital Tx signal based on the waveform information (Para. 40 “modulates” Fig. 4 item 410).
As to claim 39, Cohen discloses the apparatus of claim 26, wherein the communication interface is configured to receive RH control information from the radar processor, wherein the RH is configured to control one or more functionalities of the RH based on the RH control information (Fig. 7 CPU).
As to claim 43, Cohen discloses the apparatus of claim 26, wherein the one or more RF chains comprise a plurality of RF chains, wherein the digital radar information is in the form of a serial stream comprising an aggregation of a plurality of digital streams, the plurality of digital streams comprising digital radar information corresponding to the plurality of RF chains, respectively (Fig. 7 item 325 and 105).
As to claim 45, Cohen discloses the vehicle of claim 44, wherein the one or more RF chains comprise a Receive (Rx) chain to receive a radar Rx signal and to generate an Rx Baseband (BB) signal by processing the radar Rx signal based on the analog synchronization information (Fig. 7 item 110), wherein the digital/analog converter comprises an Analog-to-Digital (ADC) converter to convert the Rx BB signal into a digital Rx signal, wherein the communication interface is configured to transmit to the radar processor digital radar Rx information based on the digital Rx signal (Fig. 7 item 105).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 29 – 31 are rejected under 35 U.S.C. 103 as being obvious over Cohen in view of Piesinger (US 8570211 B1).
As to claim 29, Cohen does not teach the apparatus of claim 27, wherein the RH comprises a correlator configured to generate correlation information based on a correlation between the digital Rx signal and Transmit (Tx) radar information corresponding to a radar Tx signal, wherein the digital radar Rx information is based on the correlation information.
Cohen appears to suggest that correlation is done at the DSP of Fig. 7 instead of at the RF frontend receiver. See Cohen Para. 37.
Continue to claim 30.
As to claim 30, Cohen does not teach the apparatus of claim 27, wherein the RH comprises a Doppler processor configured to determine Doppler information based on the digital Rx signal, wherein the digital radar Rx information is based on the Doppler information.
In the same field of endeavor, Piesinger teaches “Signal detection processor 270 digitizes radar reflection signals using analog to digital converter (ADC) 260, cross correlates the transmit and received signals using Doppler bank of matched filters 265, and quantizes their amplitude, range, and Doppler shift using signal detector 271 (col. 4 ll. 50 – 55).”
Piesinger shows the receiver, signal detection processor and the target processor. The receiver and signal detection processor meet the scope of the claimed RH as evidenced by Applicant’s Fig. 17. The target processor meets the scope of the claimed radar processor.
In view of the teachings of Piesinger, it would have been obvious to the ordinarily skilled before filing to apply correlation and Doppler filtering to the received signal to improve signal-to-noise and mitigate clutter interference upstream the target processor (radar processor) in order to improve quality of the signal before being processed by said target processor also limiting the amount of computation needed by said processor. Also, having two processors allows for easier troubleshooting and less replacement costs if replacement were necessary because not all of the processing circuitry would need to be replaced if faulty and unrepairable.
As to claim 31, Cohen in view of Piesinger teaches the apparatus of claim 30, wherein the RH comprises an active bin selector configured to select one or more active Range-Doppler (RD) bins based on the Doppler information, wherein the digital radar Rx information is based on radar information corresponding to the active RD bins (Piesinger: Inherent to Doppler filter banks that separate, sort and filter (select) Doppler bins to isolate moving objects from clutter. Motivation to combine is the same as in claims 29 – 30. Also, the Doppler bank is down stream from the ADC as shown in Piesinger’s Fig. 7).
Claims 40 – 42 are rejected under 35 U.S.C. 103 as being obvious over Cohen in view of Lam (US 20150022386 A1).
As to claim 40, Cohen does not teach the apparatus of claim 39, wherein the RH control information comprises information to set at least one of a cutoff frequency of a Low-Pass-Filter (LPF) in the RF chain, a parameter of the digital/analog converter, or a parameter of an RF amplifier in the RF chain.
Continue to claim 41.
As to claim 41, Cohen does not teach the apparatus of claim 26, wherein the communication interface is configured to receive RH control information from the radar processor, the RH control information comprising register information to identify one or more memory registers mapped to an element of the RH, and control instructions to control one or more functionalities of the element of the RH, wherein the RH comprises a memory interface to write the control instructions to the one or more memory registers based on the register information.
In the same field of endeavor, Lam teaches “An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC (Abstract).”
In view of the teachings of Lam, it would have been obvious to allow for control of the ADC to set parameters such as sampling rate which would allow for flexible (motivation) in determining resolution for various scenarios as well as mapping to a register because registers are fast and a computer has to have memory to perform calculations and the motivation would be to have faster calculations – registers.
As to claim 42, Cohen in view of Lam teaches the apparatus of claim 41, wherein the RH comprises a controllerless RH, which is controllable based on the RH control information from the radar processor (Cohen: Fig. 7 the system clock of item 115 controls the repetition frequency of item 105).
Claim 32 is rejected under 35 U.S.C. 103 as being obvious over Cohen in view of Official notice
As to claim 32, Cohen does not teach the apparatus of claim 27, wherein the RH comprises a compressor to generate the digital radar Rx information comprising compressed Rx information based on the digital Rx signals.
A specific search of “compressor near10 digital$4” as of 7/17/2026 of Applicant’s patent publications revealed 34 hits (not including instant application) of which all but one have an appropriate published date meaning 33 valid hits of just Applicant’s own publications. Data compression is used across various technical fields (not esoteric). As such, Official Notice is appropriate. As such, the Examiner takes official notice that it would be obvious to compress data to reduce computation for transmission and reception thus reducing load requirements.
(Different Primary Reference) Claims 26 and 44 are rejected under 35 U.S.C. 103 as being obvious by Caron (US 20190210615 A1) in view of Official Notice.
As to claims 26 and 44, Caron discloses vehicle (Fig. 4) comprising:
a system controller configured to control one or more vehicular systems of the vehicle based on radar-based information (Para. 37 and item 82); and
a radar system configured to generate the radar-based information, the radar system comprising:
a radar processor (Fig. 5 item 82 microcontroller.); and
one or more Radio Heads (RHs), wherein an RH of the one or more RHs comprises::
a communication interface configured to communicate with a radar processor via a communication interconnect, wherein the communication interface is configured to receive analog synchronization information from the radar processor (Fig. 4 items 82, 46 and 78), and
to communicate digital radar information with the radar processor (Para. 38 “With such a configuration, the radar assembly and system with multifunction sensing functionality is operable to detect a speed/velocity of the object/user 21 using the Doppler Radar principles (i.e., processing by a signal processor such as the microcontroller 82 of the received reflected CW radar signal to determine frequency shifts of an emitted continuous wave indicative of the speed of the object or user or hand 21).” See discussion below.);
and one or more Radio Frequency (RF) chains to communicate radar RF signals corresponding to the digital radar information via one or more antennas (Fig. 4 items 78, 72, 60 and 36),
the one or more RF chains configured to process the radar RF signals based on the analog synchronization information (Fig. 5 items 46 and 78),
wherein an RF chain comprises a digital/analog converter to convert between an analog signal and a digital signal, wherein the analog signal corresponds to a radar RF signal communicated by the RF chain via an antenna, wherein the digital signal corresponds to the digital radar information (Fig. 5 items 42 and 80).
Caron’s Fig. 4 does not show the microcontroller receiving digital information. Caron’s citation at Para. 38 would indicate to a person of ordinary skill in the art that the microcontroller is receiving data from the radar frontend (radio head) that has been digitized. However, the disclosure does not state such even though reasonably presumed. One of ordinary skill understands that analog processing (pre-processing) is done at the frontend such as amplification, mixing and filtering. Detection, tracking, velocity determination, etc., is done via digital signal processing. Also, Caron’s disclosure at Para. 38 indicates velocity and velocity resolution is based on samples. As such, the Examiner takes official notice that it would be obvious for modern radar systems (including Caron’s) to use digital signal processing to improve detection and resolution as well as improving accuracy. Digital signal processing also allows for upgrades and changing parameters to make more robust and flexible unlike analog processing. Also, note that the exchange of information between devices implies an interface.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL W JUSTICE whose telephone number is (571)270-7029. The examiner can normally be reached 7:30 - 5:30 M-F.
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/MICHAEL W JUSTICE/Examiner, Art Unit 3648
