DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement(s) filed on November 29, 2024 have all been considered and made of record (note the attached copies of form PTO-1449).
Drawings
Eighteen (18) sheets of drawings were filed on November 29, 2024 and have been considered by the examiner.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Objections
Claims 1 and 6 are objected to because of the following informalities:
Claims 1 and 6 recite the limitation “output[ting] light input from an input port with the input port number, from an output port with an output port number corresponding to a result of a computation of the input port number”. The Examiner suggests redrafting this limitation for clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bunandar et al. (US 20190356394 A1), hereafter Bunandar.
Regarding claim 1; Bunandar teaches (see Figure 1-1) an optical computing apparatus (1-100) comprising:
an address conversion circuit (Optical Encoder 1-101) configured to convert a plurality of bit values into an address value used as an input port number (Paragraph [0094]); and
a port conversion circuit (combination of Photonic Processor 1-103 and Optical Receiver 1-105) including a shuffle circuit (Photonic Processor 1-103) configured to output light input from an input port with the input port number, from an output port with an output port number corresponding to a result of a computation of the input port number (Paragraph [0096-0097]).
Regarding claim 2; Bunandar teaches the optical computing apparatus according to claim 1. Bunandar further teaches (see Figures 1-2 and 1-5) wherein the address conversion circuit (Optical Encoder 1-101; see Figure 1-1 and 1-2) includes a plurality of Mach-Zehnder interference type optical switches (Paragraph [0111] teaches that the power tree 1-203 may be implemented using Mach-Zehnder Interferometers (MZI); see also Figure 1-5) configured to receive, as inputs, the plurality of bit values as electrical signals (Paragraph [0094] teaches that the controller 1-107 transmits the input bit string to the Optical Encoder 1-101 in the form of electrical signals).
Regarding claim 3; Bunandar teaches the optical computing apparatus according to claim 1. Bunandar further teaches (see Figures 1-2, 1-4 and 1-8) wherein the address conversion circuit (Optical Encoder 1-101) includes a plurality of branch elements (power tree 1-203; Paragraph [0108]) and a plurality of optical logic gates (VBS 1-401; see Figure 1-4 and Paragraph [0149]) configured to receive, as inputs, the plurality of bit values as optical signals.
Regarding claim 4; Bunandar teaches the optical computing apparatus according to claim 1. Bunandar further teaches (see Figure 1-1) wherein the port conversion circuit (combination of Photonic Processor 1-103 and Optical Receiver 1-105) includes a bit decomposition circuit (Optical Receiver 1-105) configured to decompose a string of bit values, corresponding to the output port number, into individual bit values (Paragraph [0098]).
Regarding claim 5; Bunandar teaches the optical computing apparatus according to claim 1. Bunandar further teaches (see Figure wherein the port conversion circuit performs (combination of Photonic Processor 1-103 and Optical Receiver 1-105), as the computation, at least one of:
a computation to generate a code bit from an information bit;
a computation to detect an error from the information bit and the code bit (Figure 2-3 and Paragraph [0272, 0279] teach act 2-102 where a computation to detect an error (2-305) is performed);
a non-linear computation in an encryption process; or
a linear computation in the encryption process.
Regarding claim 6; Bunandar teaches (see Figure 1-21 and Paragraphs [0260-0263]) an optical computing method (1-2100) executed by an optical computing apparatus (1-100; see Figure 1-1), the optical computing method (1-2100) comprising: converting a plurality of bit values into an address value (step 1-2101) used as an input port number; and outputting light input from an input port with the input port number, from an output port with an output port number corresponding to a result of a computation of the input port number (steps 1-2103 and 1-2105 constitute the computation and step 1-2107 constitutes the output and detection of the light).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mori et al. (US 20120163815 A1) discloses an optical switch device.
Meng et al. (US 20210201126 A1) discloses an optoelectronic computing system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER L KAULFUSS whose telephone number is (571)270-7260. The examiner can normally be reached Monday-Friday, 9 AM to 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571)272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER L KAULFUSS/Examiner, Art Unit 2874
/UYEN CHAU N LE/Supervisory Patent Examiner, Art Unit 2874
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