DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (US 2018/0040422).
In regards to claim 1, Shin ‘422 discloses
A thin film capacitor comprising:
a lower electrode layer (21 – fig. 3-4; [0028]) made of a metal foil ([0061-0063]);
an upper electrode layer (22 – fig. 3-4; [0028]) covering one surface of the lower electrode layer through a dielectric layer (11 – fig. 3-4; [0028]);
a passivation layer (50 & 150 – fig. 4; [0056] & [0087]) covering the one surface of the lower electrode layer so as to embed therein the dielectric layer and upper electrode layer;
first and second terminal electrodes (131a/b & 132a/b – fig. 3-4; [0028]) provided on the passivation layer;
a first via conductor (41 – fig. 3-4; [0028]) penetrating the passivation layer and connecting the first terminal electrode and the lower electrode layer; and
a second via conductor (42 – fig. 3-4; [0028]) penetrating the passivation layer and connecting the second terminal electrode and the upper electrode layer,
wherein the first terminal electrode has a planer size larger than that of the second terminal electrode (fig. 3), and
wherein the first via conductor has a sectional area larger than that of the second via conductor (fig. 3).
In regards to claim 2, Shin ‘422 discloses
The thin film capacitor as claimed in The thin film capacitor as claimed in wherein a plurality of the first via conductors (41 – fig. 3) are provided, and
wherein a sum of sectional areas of the plurality of first via conductors is larger than a sectional area of the second via conductor (fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-4, 6-7, & 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin ‘422 in view of Hiraoka et al. (US 2021/0257164).
In regards to claim 3,
Shin ‘422 fails to disclose further comprising a metal layer covering other surface of the lower electrode layer and made of a material different from the metal foil.
Hiraoka ‘164 discloses a thin film capacitor comprising: a lower electrode layer (10 – fig. 1 & 3; [0023]) made of a metal foil ([0023]); an upper electrode layer (20 – fig. 1 & 3; [0023]) covering one surface of the lower electrode layer through a dielectric layer (30 – fig. 1 & 3; [0023]); a passivation layer (42 – fig. 3; [0023]) covering the one surface of the lower electrode layer so as to embed therein the dielectric layer and upper electrode layer; wherein other surface (surface with 12 thereon – fig. 1-2; [0028]) of the lower electrode layer is higher in surface roughness than the one surface of the lower electrode layer further comprising a metal layer (12 – fig. 1-2; [0024]) covering other surface of the lower electrode layer and made of a material different from the metal foil ([0024]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the lower electrode of Shin ‘422 to have a roughness as taught by Hiraoka ‘164 to obtain a capacitor wherein the adhesion is enhanced.
In regards to claim 4,
Shin ‘422 fails to disclose wherein other surface of the lower electrode layer is higher in surface roughness than the one surface of the lower electrode layer.
Hiraoka ‘164 discloses a thin film capacitor comprising: a lower electrode layer (10 – fig. 1 & 3; [0023]) made of a metal foil ([0023]); an upper electrode layer (20 – fig. 1 & 3; [0023]) covering one surface of the lower electrode layer through a dielectric layer (30 – fig. 1 & 3; [0023]); a passivation layer (42 – fig. 3; [0023]) covering the one surface of the lower electrode layer so as to embed therein the dielectric layer and upper electrode layer; wherein other surface (surface with 12 thereon – fig. 1-2; [0028]) of the lower electrode layer is higher in surface roughness than the one surface of the lower electrode layer ([0028]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the lower electrode of Shin ‘422 to have a roughness as taught by Hiraoka ‘164 to obtain a capacitor wherein the adhesion is enhanced.
In regards to claim 6,
Shin ‘422 discloses an electronic circuit comprising: the thin film capacitor as claimed in claim 1 (see claim 1 rejection above). Shin ‘422 fails to disclose a switching element connected in parallel to the thin film capacitor.
Hiraoka ‘164 discloses a switching element (50 – fig. 3; [0031]) connected in parallel to the thin film capacitor (fig. 3; [0033]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the capacitor of Shin ‘422 into an electronic circuit as taught by Hiraoka ‘164 to obtain an electronic circuit wherein the capacitor has high-capacitance, excellent reliability, and a small size.
In regards to claim 7,
Shin ‘422 as modified by Hiraoka ‘164 further discloses wherein the switching element and the thin film capacitor are mounted on a surface of a same circuit board (fig. 3; [0033] of Hiraoka ‘164 – taking 64V, 64G, 64S & 40 to be the circuit board).
In regards to claim 9,
Shin ‘422 as modified by Hiraoka ‘164 further discloses wherein the thin film capacitor is embedded in a circuit board on which the switching element is mounted ([0031] of Hiraoka ‘164).
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin ‘422 in view of JP2019186983 hereafter referred to as Aketo.
In regards to claim 6,
Shin ‘422 discloses an electronic circuit comprising: the thin film capacitor as claimed in claim 1 (see claim 1 rejection above). Shin ‘422 fails to disclose a switching element connected in parallel to the thin film capacitor.
Aketo discloses a switching element (2 – fig. 3; [0029]) connected in parallel to the thin film capacitor (1 – fig. 3; [0029]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the capacitor of Shin ‘422 into an electronic circuit as taught by Aketo to obtain an electronic circuit wherein the capacitor has high-capacitance, excellent reliability, and a small size.
In regards to claim 7,
Shin ‘422 as modified by Aketo further discloses wherein the switching element and the thin film capacitor are mounted on a surface of a same circuit board (fig. 3; [0029] of Aketo).
In regards to claim 8,
Shin ‘422 as modified by Aketo further discloses wherein the switching element and the thin film capacitor are packaged in a same package (8; fig. 3; [0029] of Aketo).
Claim(s) 1 & 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR20050069480A hereafter referred to as Kim in view of Nishita et al. (US 2021/0226001).
In regards to claim 1,
Kim discloses a thin film capacitor comprising:
a lower electrode (22 – fig. 2; page 6 – first paragraph) layer made of a metal foil (page 3);
an upper electrode layer (24 – fig. 2; page 6 – first paragraph) covering one surface of the lower electrode layer through a dielectric layer (23 – fig. 2; page 6 – first paragraph);
a passivation layer (30 – fig. 2; page 7) covering the one surface of the lower electrode layer so as to embed therein the dielectric layer and upper electrode layer;
first and second terminal electrodes (33 – fig. 2; page 8 – first paragraph) provided on the passivation layer;
a first via conductor (32 – fig. 2; page 8 – first paragraph) penetrating the passivation layer and connecting the first terminal electrode and the lower electrode layer; and
a second via conductor (32 – fig. 2; page 8 – first paragraph) penetrating the passivation layer and connecting the second terminal electrode and the upper electrode layer,
wherein the first terminal electrode has a planer size larger than that of the second terminal electrode (fig. 2). Kim fails to disclose wherein the first via conductor has a sectional area larger than that of the second via conductor.
Nishita ‘001 discloses a thin film capacitor comprising: a lower electrode layer (40 – fig. 2; [0032]); an upper electrode layer (60 – fig. 2; [0032]) covering one surface of the lower electrode layer through a dielectric layer (50 – fig. 2; [0032]); a passivation layer (70 – fig. 2; [0032]) covering the one surface of the lower electrode layer so as to embed therein the dielectric layer and upper electrode layer; first and second terminal electrodes (80/90 – fig. 2; [0035]) provided on the passivation layer; a first via conductor (45 – fig. 2; [0035]) penetrating the passivation layer and connecting the first terminal electrode and the lower electrode layer; and a second via conductor (65 – fig. 2; [0035]) penetrating the passivation layer and connecting the second terminal electrode and the upper electrode layer, wherein the first via conductor has a sectional area larger than that of the second via conductor ([0037-0040]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the via of Kim connected to the lower electrode to have a larger area as taught by Nishita ‘001 to obtain a capacitor wherein the resistance of the vias is substantially the same.
In regards to claim 5,
Kim as modified by Nishita ‘001 discloses further comprising: another lower electrode layer (26 – fig. 2; page 6 – first paragraph of Kim) covering the upper electrode layer through another dielectric layer (25 – fig. 2; page 6 – first paragraph); and a third via conductor (32 – fig. 2; page 8 – first paragraph of Kim) penetrating the passivation layer and connecting the first terminal electrode and the another lower electrode layer, wherein the first via conductor has a sectional area larger than that of the third via conductor ([0037-0040] of Nishita ‘001).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2019/0362904 – fig. 1-3 US 2018/0122580 – 13A
US 2010/0246089 – fig. 1 US 2006/0284227 – fig. 1A
US 7,348,623 – fig. 1-2
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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/David M Sinclair/Primary Examiner, Art Unit 2847
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