DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 & 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2007242827A hereafter referred to as Nishigaki.
In regards to claim 1, Nishigaki discloses
A multilayer ceramic capacitor, comprising:
a stack including a plurality of dielectric layers (5 – fig. 2-3; [0010]) stacked on one another and a plurality of internal electrodes (7 – fig. 2-3; [0010]) located along interfaces between the plurality of dielectric layers; and
a plurality of external electrodes (3a & 3b – fig. 1; [0010]) located on outer surfaces of the stack and electrically connected to the plurality of internal electrodes,
wherein the plurality of dielectric layers comprises, as a main component, a perovskite compound containing Ba and Ti, Ba is partially optionally substituted with Ca, and Ti is partially optionally substituted with Zr ([0013]), and
a sum of resistance values of the main component and other components in the plurality of dielectric layers measured with an alternating current impedance method is greater than or equal to 1 MΩ (fig. 4-5; [0018-0019] & table 2).
In regards to claim 2, Nishigaki discloses
The multilayer ceramic capacitor according to claim 1, wherein the plurality of dielectric layers includes four constituents including cores being center portions of crystal grains of the main component and the other components, shells being outer peripheries of the crystal grains, grain boundaries, and interfaces between the plurality of internal electrodes and the plurality of dielectric layers, and the plurality of dielectric layers is represented with an equivalent circuit model in which each of the constituents is represented by a parallel circuit including a resistance R and a capacitance C and the constituents are connected in series to one another (fig. 4-5; [0018-0019] & table 2), and
a sum of R1, R2, R3, and R4 is greater than or equal to 1 MΩ, where R1 is a resistance value of the cores, R2 is a resistance value of the shells, R3 is a resistance value of the grain boundaries, and R4 is a resistance value of the interfaces measured with the alternating current impedance method (fig. 4-5; [0018-0019] & table 2).
In regards to claim 4, Nishigaki discloses
The multilayer ceramic capacitor according to claim 2, wherein R2 is greater than or equal to 200000 Ω (fig. 4-5; [0018-0019] & table 2 – When the structure recited in the references is substantially identical to that of the claims, claimed properties (resistance) are presumed to be inherent.).
Claim(s) 1-2 & 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US 2008/0266751).
In regards to claim 1, Yamazaki ‘751 discloses
A multilayer ceramic capacitor, comprising:
a stack including a plurality of dielectric layers (5 – fig. 1; [0018]) stacked on one another and a plurality of internal electrodes (7 – fig. 1; [0018]) located along interfaces between the plurality of dielectric layers; and
a plurality of external electrodes (3 – fig. 1; [0018]) located on outer surfaces of the stack and electrically connected to the plurality of internal electrodes,
wherein the plurality of dielectric layers comprises, as a main component, a perovskite compound containing Ba and Ti, Ba is partially optionally substituted with Ca, and Ti is partially optionally substituted with Zr ([0018]), and
a sum of resistance values of the main component and other components in the plurality of dielectric layers measured with an alternating current impedance method is greater than or equal to 1 MΩ (fig. 6; [0055-0057] – When the structure/method recited in the references is substantially identical to that of the claims, claimed properties (resistance) are presumed to be inherent).
In regards to claim 2, Yamazaki ‘751 discloses
The multilayer ceramic capacitor according to claim 1, wherein the plurality of dielectric layers includes four constituents including cores being center portions of crystal grains of the main component and the other components, shells being outer peripheries of the crystal grains, grain boundaries, and interfaces between the plurality of internal electrodes and the plurality of dielectric layers, and the plurality of dielectric layers is represented with an equivalent circuit model in which each of the constituents is represented by a parallel circuit including a resistance R and a capacitance C and the constituents are connected in series to one another, and
a sum of R1, R2, R3, and R4 is greater than or equal to 1 MΩ, where R1 is a resistance value of the cores, R2 is a resistance value of the shells, R3 is a resistance value of the grain boundaries, and R4 is a resistance value of the interfaces measured with the alternating current impedance method (fig. 6; [0055-0057] – When the structure/method recited in the references is substantially identical to that of the claims, claimed properties (resistance) are presumed to be inherent).
In regards to claim 4, Yamazaki ‘751 discloses
The multilayer ceramic capacitor according to claim 2, wherein R2 is greater than or equal to 200000 Ω (fig. 6; [0055-0057] – When the structure/method recited in the references is substantially identical to that of the claims, claimed properties (resistance) are presumed to be inherent).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 & 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki ‘751 in view of Woo et al. (US 2020/0126727).
In regards to claim 3,
Yamazaki ‘751 fails to disclose wherein the plurality of dielectric layers comprises 0.03 to 3 parts by mass of Sn.
Woo ‘727 discloses wherein the plurality of dielectric layers comprises 0.03 to 3 parts by mass of Sn ([0050-0051] & [0064-0069] ] – during firing Sn from the conductive paste migrates to the interface and some will migrate into the dielectric layer and based on the amount of Sn present in the conductive past the amount that migrates to the ceramic will fall with the claimed range; when the structure/method recited in the references is substantially identical to that of the claims, claimed properties (parts by mass) are presumed to be inherent).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Yamazaki ‘751 to have internal electrodes as taught by Woo ‘727 to obtain a capacitor having high reliability and high internal voltage properties by preventing discontinuity and conglomeration of an internal electrode.
In regards to claim 5,
Yamazaki ‘751 fails to disclose wherein an Sn content at the interfaces is greater than an Sn content in middle portions of the plurality of the internal electrodes.
Woo ‘727 discloses wherein an Sn content at the interfaces is greater than an Sn content in middle portions of the plurality of the internal electrodes (fig. 7; [0090-0095]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Yamazaki ‘751 to have internal electrodes as taught by Woo ‘727 to obtain a capacitor having high reliability and high internal voltage properties by preventing discontinuity and conglomeration of an internal electrode.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishigaki in view of Yamaguchi et al. (US 2018/0204678).
In regards to claim 3,
Nishigaki fails to disclose wherein the plurality of dielectric layers comprises 0.03 to 3 parts by mass of Sn.
Yamaguchi ‘678 discloses wherein the plurality of dielectric layers comprises 0.03 to 3 parts by mass of Sn (table 1).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Nishigaki to have an Sn content in the dielectric layers as taught by Yamaguchi ‘678 to obtain a capacitor with good MTTF and capacitance properties.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishigaki in view of Baik et al. (US 2022/0270822).
In regards to claim 5,
Nishigaki fails to disclose wherein an Sn content at the interfaces is greater than an Sn content in middle portions of the plurality of the internal electrodes.
Baik ‘822 discloses wherein an Sn content at the interfaces is greater than an Sn content in middle portions of the plurality of the internal electrodes ([0065]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Nishigaki to have a larger Sn content near the interface as taught by Baik ‘822 to obtain a capacitor with improved withstand voltage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2009/0059471 – fig. 4; [0035] US 2016/0196919 – [0093]
US 2010/0220427 – claim 1 US 2023/0071958 – abstract
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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/David M Sinclair/Primary Examiner, Art Unit 2847
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