Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FLEMING, JR. et al. US PG-Pub 2018/0189231 A1 (hereinafter Fleming).
As per claim 1, Fleming teaches a computing circuit comprising:
a plurality of reconfigurable processing elements (PEs) (Para. 0072, 0079 and Fig. 1, PEs);
data communication lines directly connecting an output port of each of the PEs with an input port of each other PE of the plurality of PEs (Para. 0072 and 0084-0088, interconnect network between PEs; switch boxes (SBs) and inter-column switch boxes (ICSBs); circuit-switched, statically configured data-path wires and point-to-point channels; multicast and configurable muxes; see also Fig. 6; see also paragraphs 0101-0103 and 0117 which discloses point to point communication channels formed as virtual circuits between PEs; PEs communicate over dedicated “dedicated virtual circuits,” and Fleming expressly characterizes the PE communications as “direct.” Fleming also describes mux-controlled paths forming fixed electrical paths between communicating PEs.);
wherein the computing circuit is configured to execute a data flow model by configuring at least a subset of PEs of the plurality of PEs to perform a respective discrete computation implementing the data flow model (Para. 0075, 0081-0083 and Fig. 3A-3C; dataflow graph overlay; mapping kernels to physical data paths; sequencer/configuration controllers; PEs act as dataflow operators once configured); and
wherein the subset of PEs includes a first PE and one or more destination PEs, the first PE being configured to perform its respective discrete computation on receipt of a ready to receive output signal from the one or more destination PEs (Para. 0081, 0102 and 0107-0108; ‘ready signal’; Further Fleming identifies producers PEs and downstream consumer PEs. The producer’s output is steered through the data path to one or multiple consumer endpoints, including multicast to multiple destination PEs).
As per claim 2, Fleming teaches the computing circuit of claim 1, wherein the one or more destination PEs are configured to perform a computation using the output of the first PE according to the data flow model (Para. 0075, 0091-0092 and Fig. 3A-3C, PEs are dataflow operators; outputs of one PE are routed to downstream PEs and consumed by those PEs to perform their computation).
As per claim 3, Fleming teaches the computing circuit of claim 1 further comprising an operand memory provided for each PE to store a plurality of input operands; wherein the first PE is configured to perform the discrete computation after determining the receipt of all input operands of its respective discrete computation in its operand memory (Para. 0091-0092 and 0122-0124; PEs include input buffers/ingress buffers and local storage (input buffers, registers) to receive/hold operands; scheduler triggers PE execution only when inputs present and egress buffer space available; see also Fig. 9).
As per claim 4, Fleming teaches the computing circuit of claim 3, wherein the operand memory implements a first in first out (FIFO) queue to store the input operands (Para. 0080-0081, 0116 and 0209-0216; The CSA describes FIFO/queue semantics for input/output channels and staging buffers (latency‑insensitive channels, input queues, use of FIFOs/gasket memory as FIFO buffers); The RAF / input queue examples also show FIFO/completion buffer behavior; see also Fig.31–33)
As per claim 5, Fleming teaches the computing circuit of claim 4, wherein while the FIFO queue of a first destination PE is not full, the first destination PE transmits a ready to receive output signal to each other PE of the plurality of PEs (Para. 0108-0113, 0092 and 0116; Explicit backpressure / ready signaling: consumer endpoints assert readiness to accept data; flow‑control path conveys ready/valid back to producers so producers only send when sinks are ready; Furthmore, Fleming’s flow-control network is configurable and capable of using switch or mux structures similar to the forward data network. Its network is boundless and spans the entire fabric, with any PE capable of communicating with any other PE; see also table 1).
As per claim 6, Fleming teaches the computing circuit of claim 3, wherein the receipt of all input operands is determined in every processing cycle by the first PE (Para. 0116, 0091-0092 and Fig. 9; PE scheduler checks ingress buffers each cycle and executes when all inputs present; PE execution proceeds based on immediate availability of inputs and output‑buffer availability — the scheduler examines buffer status “each cycle”)
As per claim 7, Fleming teaches the computing circuit of claim 3, wherein each input operand is stored in a register; and the register is populated by a multiplexer connected to data communication lines transmitting data from output port of each of the PEs (Para. 0091-0092, 0116, 0122-0124; PE internal registers / input registers and muxing of network inputs into PE inputs are described: PEs have input buffers, muxes to select input channels, and network‑steered inputs; see also Fig. 9)
As per claim 8, Fleming teaches the computing circuit of claim 7, wherein a said PE is designated as input, and each multiplexer is configured to populate the operand memory using output of one of the PEs based on a reconfigurable source index register comprising an index information of the said PE designated as input (Para. 0156-0164, 0103, 0107 and Fig. 23A-23C; CSA describes configurable routing (static/circuit‑switched mux selection), configuration registers / configuration packages loaded to steer muxes, and reconfigurable source selection (sequencer / LCC programs muxes)).
As per claim 9, Fleming teaches the computing circuit of claim 1, wherein an output of each PE is transmitted to each other said PE over the data communication lines in a single processing cycle (Para. 0103, 0110-0116 and 0119-0123; CSA teaches very low‑latency local circuit‑switched channels and describes the inter‑PE paths designed for single‑cycle or zero/one‑cycle latency between adjacent PEs and the broadcast/multicast to many PEs in one cycle across local networks; Furthermore, Fleming states that its network may be boundless, meaning that it spans the entire fabric and that “one PE is to communicate with any other PE.”)
As per claim 10, Fleming teaches the computing circuit of claim 1, wherein each PE comprises an arithmetic logic unit (ALU) to perform its respective discrete computation and an Opcode register storing a code designating the respective discrete computation to be performed by the ALU (Para. 0091, 0116, 0105-0106; PEs include ALU functional units and operation configuration/control registers (operation config words, opcode registers) loaded during configuration; see also Fig. 9 operation configuration register and ALU).
As per claim 11, Fleming teaches the computing circuit of claim 1, wherein each PE is configured to receive in its memory input operands for a subsequent computation while performing its respective discrete computation (Para. 0116, 0122-0124, 0105; CSA describes PEs supporting pipelined operation and the ability to accept new inputs (ingress buffering) while performing current operation; overlapping load of next operands while computing).
As per claim 12, Fleming teaches the computing circuit of claim 1, further comprising one or more external memory controllers configured to:
receive request from a requesting PE among the plurality of PEs for loading data stored in an external memory; query the external memory based on the received requests: obtain a response from the external memory; and provide the obtained response to the requesting PE (Para. 0119-0128; RAF circuits / memory controllers / Accelerator Cache Interconnect that accept PE requests, issue memory requests, arbitrate responses, and return loads to PEs; completion buffers reorder responses to request order; see also Fig. 10–11).
As per claim 13, Fleming teaches the computing circuit of claim 1, wherein the data flow model is a control dataflow graph (CDFG) (Para. 0075, 0091; CDFG).
As per claim 14, Fleming teaches a method of executing a data flow model, the method comprising:
providing the computing circuit of any one of claims 1; configuring at least a subset of the plurality of PEs of the computing circuit to perform a plurality of discrete computation implementing the data flow model; and triggering execution by the computing circuit (Para. 0156-0164, 0136-0144; Configuration and execution flow described: sequencer/LCC loads config, config cache/prefetch modes, then fabric executes dataflow graph when configured; see also Fig. 13).
As per claim 15, it’s rejected for the same reasons set forth above in claim 1. Further Fleming CSA explicitly describes main memory, RAF/memory controllers, MPs, SBs, circuit‑switched networks supporting multicast/broadcast, homogeneous PE arrays (or configurable heterogeneous arrays) and broadcast/multicast capability, and description that PEs can be connected such that data can be routed/broadcast to many PEs (Para. 0072, 0116, 0125-0130).
As per claims 16-20 – each is a method claim that depends on earlier apparatus claim. Each reference apparatus claim mapped above; Flemming CSA supplies the same configuration plus execute method for each such apparatus (Para. 0156-0164, 0176-0183 and Fig. 23-25).
Claims 1 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mohapatra et al. US PG-Pub 2020/0134417 A1 (hereinafter Mohapatra).
As per claim 1, Mohapatra teaches a computing circuit comprising:
a plurality of reconfigurable processing elements (PEs) (Fig. 1, array of PEs 105a-i, reconfigurable via configurable registers 120; see also para. 0024-0026);
data communication lines directly connecting an output port of each of the PEs with an input port of each other PE of the plurality of PEs (Para. 0028 and 0039-0040, inter-PE data paths, buses 140a-c, tensor data distribution unit 130; Furthermore, Mohapatra discloses partial-sum transfer between neighboring PEs. A PE accepts a partial sum from a permitted neighbor in either the horizontal or vertical direction, see paragraph 0061 and Fig. 12);
wherein the computing circuit is configured to execute a data flow model by configuring at least a subset of PEs of the plurality of PEs to perform a respective discrete computation implementing the data flow model (Para. 00025-0026 and 0056-0057; descriptors in configuration registers 170 define dataflow schedules); and
wherein the subset of PEs includes a first PE and one or more destination PEs, the first PE being configured to perform its respective discrete computation on receipt of a ready to receive output signal from one or more destination PEs (Para. 0041-0042, 0061 and 0065; FSM 175 controls load/compute based on availability; descriptor fields like PEColActv/PERowActv and accumulation control signals; Furth more, Mohapatra permits neighboring PEs to contribute partial sums and therefore provides source and receiving PE relationships).
As per claim 15, it’s rejected for the same reasons set forth above in claim 1. The architecture, descriptors, multiplexers, broadcasting, and steps are disclosed in paragraph 0024-0042.
Response to Arguments
Applicant's arguments filed 1/16/2026 have been fully considered but they are not persuasive. In claim 1, applicant argues that Fleming employes a tile-based mesh having shared switch boxes and multiple hops whereas amended claim 1 allegedly requires a dedicated, switchless, contention-free, all-to-all bypass network having a separate physical line for everyone pair of PEs.
The argument is not persuasive because it relies on restrictions that are not explicitly recites in claim 1. Claim 1 does not expressly require: a separate uninterrupted physical conductor for every ordered PE pair; elimination of multiplexers or switches; simultaneous transmission by every PE; zero latency and others. The phrase “data communication lines directly connecting” does not, by itself, exclude a statically configured circuit-switched path. Fleming expressly discloses that PEs communicate over dedicated virtual circuits formed by statically configuring a circuit-switched communication network and characterizes communication in the architecture as “direct.” Fleming further teaches configurable network multiplexer that form dedicated circuit-switched paths between channel endpoints and fixed electrical paths between communicating PEs.
Applicant’s argument that Fleming employs a static timetable is also not persuasive. The runtime execution of Fleming is data-driven. Fleming teaches that a PE executes when the required operands have arrived and when space is available for the output, and that downstream consumer assert readiness through a reverse flow-control path.
In claim 2, applicant argues that Fleming requires output buffers, while the claimed architecture allegedly does not require output buffers. The argument is not persuasive because neither claim 1 nor claim 2 exclude output buffers. Claim 2 merely requires the destination PEs to perform computation using the output of the first PE according to the dataflow model. Fleming expressly teaches that the output of an upstream PE is transported to a downstream PE and consumed by the downstream PE as an operand for its configured dataflow operation. The presence of an output buffer does not prevent the upstream output from being directly communicated over the configured channel and does not distinguish the claimed function.
In claims 3 and 4, applicant argues that the claimed architecture broadcasts a result only when all destination PEs are ready. Also, applicant argues that Fleming does not use the term FIFO.
The arguments are not persuasive. Claim 3 does not recites a global broadcast to all PEs. Fleming expressly teaches multicast operation in which a source does not assert valid data until a ready signal is received from each sink. Furthermore, Fleming discloses registered PE input buffers operating with in-order, thus is a FIFO.
In claim 5, applicant argues that Fleming’s ready or backpressure signal travels through switch boxes and is returned only to a particular producer, rather than being transmitted to each other PE. Fleming expressly discloses that a downstream PE or consumer endpoint transmits a ready or space-available signal when its input buffer has room to accept additional data. Fleming also discloses a separate configurable flow-control network that spans the PE fabric, see table 1.
In claims 6 and 7, Applicant argues that the claimed PE does not require a scheduler or a multiplexer and the multiplexer in claim 7 is different from the prior art as far as the selection. The argument is not persuasive. Fleming states that each cycle the scheduler may select an operation based upon the availability of the input and output buffers. Furthermore, Fleming network includes multiplexers 702, 704 and 706 configured to steer data from producer PE output paths to consumer PE input paths. Data entering the receiving PE from the location network is registered in an input buffer for subsequent operation. Thus, the network multiplexer connected to the PE communication lines selects an output path from a producer PE and populates the receiving PE’s registered input buffer.
In claims 8 and 9, Applicant argues that Fleming does not disclose a source-index register or and that the prior art discloses only one PE communicating with another PE, rather than all PEs transmitting simultaneously to all other PEs. The arguments are not persuasive Fleming store configuration information controlling the network multiplexers and identifying which PE output is selected for a destination input. Such stored source-selection information reasonably corresponds to the claimed source index. Furthermore, claim 9 does not require simultaneous all-to-all transmission. Fleming expressly teaches a boundless network in which any PE can communicate with any other PE in a single cycle and further supports multicast communication.
In claim 10, Applicant’s argument regarding Fleming’s routed network do not address the added limitations. Fleming expressly discloses ALU 918 and an operation-configuration register storing an opcode that designates the computation performed by the ALU.
In claim 14, Applicant acknowledges that Fleming performs substantially the claimed configuration and execution steps but argues that Fleming uses a different implementation. The claim does not exclude Fleming’s implementation. Fleming configures selected PEs to implement a dataflow graph and subsequently triggers execution when the required operands and readiness conditions are satisfied.
Applicant argues that Mohapatra is limited to CNN processing using specialized PEs, column buses, neighboring-PE connections, and predetermined processing phases. According to Applicant, Mohapatra therefore does not disclose the direct all-to-all connectivity, ready-to-receive signaling, dynamic data-driven execution, or broadcast architecture required by claim 1 and 15.
Applicant arguments are not persuasive. Claims 1 and 15 do not exclude CNN processing, require general-purpose PEs, or prohibit buses, multiplexers, buffers, or programmed processing phases. Mohapatra discloses reconfigurable PEs configured by descriptors and control signals to perform respective portions of a dataflow schedule. Mohapatra’s buses, programmable input paths, and inter-PE connections provide selectable communication and broadcast capability under the broadest reasonable interpretation. Its destination-related enable and accumulation signals reasonably correspond to the claimed ready-to-receive signal. Mohapatra also discloses identically designed PEs and a data-distribution until that transfers data between memory and the PEs.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PG-Pub 2020/0210172 teaches dynamic configuration of data flow array for processing data in a plurality of processing elements.
US PG-Pub 2019/0057060 teaches reconfigurable fabric data routing.
US PG-Pub 2018/0267929 teaches reconfigurable parallel processing.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
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