I still haven’t beaten silkson
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claims 1-18 canceled with Prel. Amdt filed 03-28-25.
Specification
The disclosure is objected to because of the following informalities:
Please re-arrange the following in the specification before the detailed Description:
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S): See MPEP § 608.01(f). A reference to and brief description of the drawing(s) as set forth in 37 CFR 1.74.
Also, any prior art drawings should be labeled: “Prior Art”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19, 20, 22-27, 33-35 and 36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vliex et al.(AppAdmittedPriorArt cite: NPL Bias Voltage DAC operating a cryogenic temperature for solid state Qubit Applications: IIISSC Letters, IEEE, Vol.3, 22 July 2020).
Re claims 19 and 35:
The reference to Vliex et al shows a biasing DAC arrangement for supplying a S&H circuit, see figure below with notations, figure 2 shows the general concept, and figure 3b showing the extended bias range that allows for a voltage ramp generation coupled via series terminals; each terminal is coupled upstream from the voltage ramp generator via a sample-and- hold circuit (multiple S&H) for holding a sampled voltage, and a controller (see 6 bit ctrl line)
allowing a switch to each sample-and-hold circuit at a set time to the voltage ramp generator to set the sampled voltage as the set bias voltage, with the voltage ramp generator adapted to provide the voltage ramp spanning required set bias voltage range.
The method steps being inherent.
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Re claim 20 : As noted, there is a periodical refresh of each output channel, where a switch control signal, inherent, is adapted to switch said sample-and-hold circuit periodically to couple to said voltage ramp and counteract parasitics, such as leakage(see p.2., col.1).
Re claim 22: the voltage ramp generator comprises a digital-to-analogue converter (DAC), see figures above, having an output coupled to each of said series of terminals Vu,VL for providing the set bias voltage to each terminal.
Re claim 23: As shown in the figure 2 and 3b, the voltage ramp generator comprises an integrating (i.e., capacitor input elements)digital-to-analogue converter (DAC), in particular switched multiple input capacitors(LSB,MSB caps).
Re claim 24: The voltage ramp generator shows switched-capacitor implementation for the integrating, digital-to-analogue converter (DAC) that allows adjustment of the slope output(see figure 2 as labeled).
Re claim 25:
The voltage ramp generator is adapted allowing complete skipping of voltage ranges by way of switched selections in the DAC with MUX(see fig 3b).
Re claim 26:
The voltage ramp generator comprises a switched capacitor integrator, as noted above, forming the DAC, see figures above.
Re claim 27: The voltage ramp generator comprises a variable input capacitance(switched cap, see figure 2), dynamically changing the slope of the voltage ramp.
Re claim 33: as shown in figure 3b, a MUX is present at the biasing input and to feed, downstream, the multiple Sample-and-hold circuits, a DEMUX would be inherent, see figure 2.
Re claim 34: The ability to scale the implementation for many qubits, with the sample-an-hold circuits and voltage ramp generator, is made possible by using an integrated circuit as opposed to discrete electronics, see intro paragraph(see page 1 of article, left col.)
Re claim 36: the system as noted in the title, figures and introduction, specifically proposes this scalable DAC and biasing for providing a series of set voltages to a series of cryogenic components in quantum computing devices implementing spin qubits/ quantum dots/ quantum-dot based qubits, for example, see figure 2, load at cryogenic temps.
Allowable Subject Matter
Claims 21, 28-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ARNOLD M. KINKEAD
Primary Examiner
Art Unit 2849
/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2849 “