CTNF 18/871,404 CTNF 80774 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-30-03-h AIA Claim Interpretation 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. 07-30-07 This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: means for communicating with a display controller , means for providing display data in claim 17. Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof. If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function. Contingent Limitations Claim 9 recites the following contingent limitations: configuring a first physical layer circuit powered by a first power supply to: A) communicate first frames of data at a first data rate over a first serial bus to a display controller when the display controller is operated in a high-speed mode , and B) refrain from communicating over the first serial bus when the display controller is operated in a low-power mode ; C) configuring a second physical layer circuit powered by a second power supply to communicate second frames of data at a second data rate over a second serial bus to the display controller when the display controller is operated in the low-power mode; D) configuring a first processor to generate the first frames of data, the first processor being powered by the first power supply; and E) configuring a second processor to provide the second frames of data to the second physical layer circuit when the display controller is operated in the low-power mode, the second processor being powered by the second power supply. These limitations are contingent because they recite steps that are only required to be performed if their conditions are met. Limitations A, B, C, and E only need to be performed if the respective condition of operating in high-speed mode or a low-power is true. While these conditions may be mutually exclusive, there is nothing in the claim language that logically requires them to be so. The broadest reasonable interpretation (BRI) of the claim language includes the possibility that neither condition is true, which would include embodiments of the method where none of the steps associated with the conditions are performed. Because limitation D is recited as being unconditional, the BRI of claim 9 requires the execution of only one of either: limitation D, limitations A and D, or limitations B, C, D, and E. Similar reasoning may be applied to the dependent claims. Claim 10 is further limits limitation A, while claims 11-13 further limits limitations B, C, and E. Claims 14-16 are unconditional and therefore further limit A, B, C, D, and E. This interpretation only applies to claims 9-16. The remaining claims are directed to an apparatus which must include structures for performing all of the conditional steps even when the conditions are not true. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 24-30 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because they include transitory media. Claims 24-30 are rejected because the Applicant has not provided evidence that the term “processor-readable storage medium” (PRSM) excludes non-statutory subject matter. The broadest reasonable interpretation (BRI) of PRSM includes both transitory and non-transitory media. The specification describes a computer-readable medium as including “…a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions…” [para. 0091] . The specification also describes a PRSM as including a non-transitory medium [para. 0105] , but this description is open-ended and does not explicitly restrict the PRSM to only non-transitory embodiments. Absent an explicit and deliberate limiting definition, or a clear differentiation between non-transitory and transitory media in the disclosure, the words "storage", "recording", “tangible”, etc. are insufficient to convey only statutory embodiments to one of ordinary skill in the art. Therefore, the claims are directed towards non-statutory subject matter since PRSM may be interpreted to include transitory media. Transitory media cannot be classified as a machine, process, article of manufacture, or composition of matter as required by 35 U.S.C. 101. The Examiner recommends that all instances of PRSM be amended to specifically recite non-transitory media. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 9 and 14-16 are rejected under 35 U.S.C. 10(a)(1) as being anticipated by Connell et al., U.S. Patent Application Publication No. 2014/0267316. Connell was originally cited in the IDS filed by Applicant on 7 April 2026. Regarding claim 9, Connell discloses a method comprising: configuring a first physical layer circuit powered by a first power supply to: communicate first frames of data at a first data rate over a first serial bus to a display controller when the display controller is operated in a high-speed mode [contingent] , and refrain from communicating over the first serial bus when the display controller is operated in a low-power mode [contingent] ; configuring a second physical layer circuit powered by a second power supply to communicate second frames of data at a second data rate over a second serial bus to the display controller when the display controller is operated in the low-power mode [contingent] ; configuring a first processor to generate the first frames of data [para. 0016: “These graphic rendering capabilities allow the application processor 104 to render graphic or display data at high frame rates , and may be provided by a dedicated graphics processing unit (GPU) associated with the application processor 104.”] , the first processor being powered by the first power supply [abstract: “Most of these types of computing devices, however, draw power from battery-based supplies that provide limited amounts of power between charges.”] ; and configuring a second processor to provide the second frames of data to the second physical layer circuit when the display controller is operated in the low-power mode, the second processor being powered by the second power supply [contingent] . Regarding claim 14, Connell teaches that the first physical layer circuit is further configured to operate in accordance with Mobile Industry Processor Interface (MIPI) Alliance display serial interface (DSI) protocols [Fig. 3: MIPI Port 316] . Regarding claim 15, Connell teaches that the second physical layer circuit [SPI Port 346] is further configured to operate in accordance with serial peripheral interface (SPI) protocol, a Camera Control Interface (CCI) protocol, an Inter-Integrated Circuit (I2C) protocol, an Improved Inter-Integrated Circuit (I3C) protocol or a system power management interface (SPMI) protocol [para. 0028: “In such cases, the low-power processor 204 transmits display data using a generic communication protocol. This generic communication protocol may be compliant with any suitable specification or standard, such as serial peripheral interface (SPI) , system management bus (SMBus), or an I2C communication protocol .”] . Regarding claim 16, Connell teaches that the second processor [low-power processor 304] is further configured to communicate with a touch panel interface [display 324; para. 0078: “Alternatively or in addition, the display system can be an integrated component of the example electronic device, such as part of an integrated touch interface. ”] over the second physical layer circuit [Fig. 3: SPI port 346] . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-30 are rejected under 35 U.S.C. 103 as being unpatentable over Connell et al., U.S. Patent Application Publication No. 2014/0267316, in view of Zou et al., U.S. Patent Application Publication No. 2022/0045611 . Regarding claim 1, Connell discloses a device [Fig. 3] comprising: a display controller [frame buffer 328 and MIPI Port 326] coupled to a display panel [display 324] ; a first physical layer circuit [MIPI port 316 of application processor 302] powered by a first power supply and configured to: communicate first frames of data at a first data rate [para. 0016: “These graphic rendering capabilities allow the application processor 104 to render graphic or display data at high frame rates , and may be provided by a dedicated graphics processing unit (GPU) associated with the application processor 104.”] over a first serial bus to the display controller [MIPI Data- 318 and MIPI Data+ 320 supplied from MIPI Port 316] when the display controller is operated in a high-speed mode [switching to low power processor 304 enters a low speed mode, indicating a high speed mode when used with application processor; para. 0017: “The low-power processor 106 may be implemented as a reduced-instruction set computing (RISC) processor which… operates at a lower frequency… than the application processor 104. ”; para. 0030: “When a computing device enters a state of low graphical activity, a refresh-frequency of visual content of the display 218 may decrease such that the low-power processor 204 can render the visual content . In some embodiments, the display manager 216 may determine when to transition control of, or access to, the display 218 from the application processor 202 to the low-power processor 204 .”] , and refrain from communicating over the first serial bus when the display controller is operated in a low-power mode [para. 0033: “…the display manager 216 transfers control of the display 218 to the low-power processor 204… the display manager 216 switches the input selection of the de-multiplexor 224 to receive data from the low-power processor 204 instead of the application processor 202 . ; a second physical layer circuit [SPI Port 346 of low power processor 304] powered by a second power supply and configured to communicate second frames of data at a second data rate [para. 0030; para. 0033: “The low-power processor 204 then generates additional display data based on the data stored in the display control registers 212… The low-power processor 204 then transmits the additional display data to the protocol converter 228 via the generic data bus 226.”] over a second serial bus to the display controller when the display controller is operated in the low-power mode [para. 0030, 0031: application processor is placed in low power mode, low power processor takes over graphics data transmission to frame buffer thereby constituting a low power mode for the frame buffer and MIPI port 326] ; a first processor powered [application processor 302] by the first power supply and configured to generate the first frames of data; and a second processor powered [low-power processor 304] by the second power supply and configured to provide the second frames of data to the second physical layer circuit when the display controller is operated in the low-power mode. Connell does not disclose a first physical layer circuit and first processor powered by a first power supply and a second physical layer circuit and second processor powered by a second power supply . Zou discloses a first processor powered by a first power supply and a second processor powered by a second power supply [Fig. 11: CPU and GPU with respective second-stage voltage conversion circuit; para. 0075: “For example, as shown in FIG. 11, because voltage requirements of different loads are different, to refine power supply management and improve power supply efficiency, a plurality of second-stage voltage conversion circuits 22 may supply power to different loads (for example, the CPU, the GPU , the AI processor, and the memory)... Therefore, the second-stage voltage conversion circuit 22 may be integrated with the load to which the second-stage voltage conversion circuit 22 supplies power, so that the power supply circuit is more integrated and has a higher power density.”] . It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Connell and Zou by including a first power supply and a second power supply to power the first processor and second processor (i.e., the application processor and low power processor of Connell), as taught by Zou. Connell and Zou are both directed to systems that employ a plurality of processing units. Connell discloses that the application processor and low power processor have different power consumption profiles [para. 0012: “As described above, full-power processors, such as application processors and dedicated graphics engines, consume considerable power relative to other components of a computing device ... Embodiments of display co-processing enable a lower-power processor (e.g., micro-controller) to transmit additional display data to a display to effectively render visual content while a full-power processor remains in a low-power or sleep state.”] . Zou discloses a system with a plurality of processors having different power requirements, and further teaches that each processor may have its own power source (i.e., a second-stage voltage conversion circuit). The application of Zou’s power supplies to Connell is motivated by Zou’s teaching that the integration of respective power supplies to loads with different power requirements improves power management, power supply efficiency, circuit integration, and power density [para. 0075] . Additionally, because Connell teaches that the first and second physical layer circuits are integrated with the first and second processors, respectively, powering the first and second processors with the first and second power supplies also supplies power to the first and second physical layer circuits. Regarding claim 2, because Connell teaches that the first processor operates at a higher power level than the second processor, and because Zou discloses voltage conversion circuits supplying power to respective loads, the combination of Connell and Zou teaches that the first power supply provides power in the high-speed mode at a voltage that is greater than a voltage at which the second power supply provides power. Regarding claim 3, Zou discloses that a voltage at which the first power supply provides power is reduced when the display controller is operated in the low power mode [para. 0113: “In addition, the output voltage of the first-stage voltage conversion circuit 21 is increased when the load runs the high-performance service, and the output voltage of the first-stage voltage conversion circuit 21 is decreased when the load is in the low power consumption state , so that power supply efficiency of the power system is higher.”] . It would have been obvious to one of ordinary skill in the art to further combine the teachings of Zou and Connell by modifying Connell to include a first-stage voltage conversion circuit as taught by Zou. The application of Zou’s first-stage voltage conversion circuit to Connell is motivated by Zou’s teaching that the adjustment of the voltage provided to the second stage conversion circuit increases power supply efficiency. Regarding claim 4, Connell teaches that the first processor is further configured to enter a dormant mode when the display controller is operated in the low-power mode [para. 0031: “The application processor 202 can then enter a low-power state to conserver power. In some cases, the low-power state may prevent the application processor 202 from rendering display data because doing so consumes considerable power.”] . Regarding claim 5, because Connell’s MIPI Port 316 is integrated with the application processor, and because Connell teaches that the demultiplexer selects the output of the protocol converter 354 in place of the MIPI Port 316 when the application processor in a low power mode, Connell teaches that the first physical layer circuit is further configured to enter a dormant mode when the display controller is operated in the low-power mode. Regarding claim 6, Connell teaches that the first physical layer circuit is further configured to operate in accordance with Mobile Industry Processor Interface (MIPI) Alliance display serial interface (DSI) protocols [Fig. 3: MIPI Port 316] . Regarding claim 7, Connell teaches that the second physical layer circuit is further configured to operate in accordance with serial peripheral interface (SPI) protocol, a Camera Control Interface (CCI) protocol, an Inter-Integrated Circuit (I2C) protocol, an Improved Inter-Integrated Circuit (I3C) protocol or a system power management interface (SPMI) protocol [para. 0028: “In such cases, the low-power processor 204 transmits display data using a generic communication protocol. This generic communication protocol may be compliant with any suitable specification or standard, such as serial peripheral interface (SPI) , system management bus (SMBus), or an I2C communication protocol .”] . Regarding claim 8, Connell teaches that the second processor is further configured to communicate with a touch panel interface over the second physical layer circuit [para. 0078: “Alternatively or in addition, the display system can be an integrated component of the example electronic device, such as part of an integrated touch interface. ”] . Claims 9-30 are directed to the same features as claims 1-8, and are rejected on the same basis . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kwa et al., U.S. Patent No. 9,865,233, discloses a display coupled to a first and second physical layer circuit communicating frames from a first or second processor over a first or second bus based on a first or second mode [Fig. 2] . Gulati et al., U.S. Patent Application Publication No. 2016/0054773, discloses a processor with a GPU and processor core receiving unique power supply voltages [para. 0025; Fig. 2] . Nikazm et al., U.S. Patent No. 8,812,748, discloses a display interface configured to select between a digital and analog interface [Fig. 5] . Ha et al., U.S. Patent Application Publication No. 2013/0111241, discloses a display that reduces the rate frames are displayed when operating in a low power mode [para. 0010] . Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI H BAE whose telephone number is (571)272-7181. The examiner can normally be reached Tuesday to Friday and every other Monday, 9 am to 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office Phone: 571-272-7181 Fax: 571-273-7181 ji.bae@uspto.gov Application/Control Number: 18/871,404 Page 2 Art Unit: 2176 Application/Control Number: 18/871,404 Page 3 Art Unit: 2176 Application/Control Number: 18/871,404 Page 4 Art Unit: 2176 Application/Control Number: 18/871,404 Page 5 Art Unit: 2176 Application/Control Number: 18/871,404 Page 6 Art Unit: 2176 Application/Control Number: 18/871,404 Page 7 Art Unit: 2176 Application/Control Number: 18/871,404 Page 8 Art Unit: 2176 Application/Control Number: 18/871,404 Page 9 Art Unit: 2176 Application/Control Number: 18/871,404 Page 10 Art Unit: 2176 Application/Control Number: 18/871,404 Page 11 Art Unit: 2176 Application/Control Number: 18/871,404 Page 12 Art Unit: 2176 Application/Control Number: 18/871,404 Page 13 Art Unit: 2176
Prosecution Insights