Prosecution Insights
Last updated: April 19, 2026
Application No. 18/871,435

SOLID-STATE IMAGING DEVICE

Non-Final OA §102§103
Filed
Dec 03, 2024
Examiner
GILES, NICHOLAS G
Art Unit
2639
Tech Center
2600 — Communications
Assignee
Sony Semiconductor Solutions Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
98%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
683 granted / 834 resolved
+19.9% vs TC avg
Strong +16% interview lift
Without
With
+16.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
25 currently pending
Career history
859
Total Applications
across all art units

Statute-Specific Performance

§101
4.0%
-36.0% vs TC avg
§103
39.2%
-0.8% vs TC avg
§102
24.4%
-15.6% vs TC avg
§112
23.7%
-16.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 834 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (U.S. Pub. No. 20140374572). Regarding claim 1, Kim discloses: A solid-state imaging device comprising: a plurality of pixels (pixel array 500 may include a plurality of unit pixels P 10 arranged in rows and columns detecting visible light, par. 25, 118, and Fig. 8); and a control circuit (control unit 850, par. 83, 128 and Figs. 1 and 8), wherein each of the plurality of pixels includes: a photoelectric conversion element that performs photoelectric conversion on incident light to generate an electrical signal (photoelectric conversion unit 100 included in each of the unit pixels 10 may generate the photo-charges having an amount corresponding to the intensity of the incident light and provide the photo-charges to the first node N1, par. 127 and Figs. 3 and 4); a first pixel circuit that converts the electrical signal into first information (first signal generation unit 300b may generate the analog signal AS in the first operation mode based on the amount of the photo-charges accumulated in the first node N1, par. 74-82, 126, and Fig. 4); and a second pixel circuit that converts the electrical signal into second information (in mode control unit 200a the switch 230 is turned off in the second operation mode during which the mode signal MD has the second logic level, where the mode signal MD is provided from the control unit 850, and the first NMOS transistor 210 discharges the photo-charges generated from the photoelectric conversion unit 100 through the first NMOS transistor 210 to generate the sensing current IS, and the amplifier 220 generates the sensing voltage VS having a magnitude logarithmically proportional to the magnitude of the sensing current IS and provides the sensing voltage VS to the gate of the NMOS transistor 210, where since an amount of the photo-charges generated from the photoelectric conversion unit 100 and accumulated in the first node N1 is proportional to the intensity of the incident light, the magnitude of the sensing current IS generated from the first NMOS transistor 210 in the second operation mode and the magnitude of the sensing voltage VS generated from the amplifier 220 in the second operation mode may be proportional to the intensity of the incident light, and second signal generation unit 400 generates an on signal ONS and an off signal OFFS based on a change of the sensing voltage VS in the second operation mode, where the motion detection unit 700 may detect a motion of a subject based on the on signal ONS and the off signal OFFS provided from each of the unit pixels 10 to generate a direction signal DIRS representing a moving direction of the subject and a speed signal SPS representing a speed of the subject (considered motion/event detection information), par. 56, 59, 62-64, 84, 85, 101-107, 118, 122, and Figs. 2, 4-6 and 8), and the control circuit controls each of the plurality of pixels such that the photoelectric conversion element is connected to either the first pixel circuit (in the first operation mode control unit 850 provides an activated transmission control signal TX to the transmission transistor 311 of first signal generation unit 300b to turn on the transmission transistor 311, where the photo-charges accumulated in the first node N1 are transferred to the floating diffusion area FD through the transmission transistor 311, par. 75, 130, and Fig. 4) or the second pixel circuit (when mode signal MD provided by control circuit 850 has the second logic level the switch 230 of mode control unit 200a is turned off in the second operation mode, and the first NMOS transistor 210 discharges the photo-charges generated from the photoelectric conversion unit 100 through the first NMOS transistor 210 to generate the sensing current IS, and the amplifier 220 generates the sensing voltage VS having a magnitude logarithmically proportional to the magnitude of the sensing current IS, par. 56, 59, 62-64, 84, 85, 101-107, 118, 122, and Figs. 2, 4-6 and 8). Regarding claim 2, Kim further discloses: control circuit controls, on a basis of arrangement of each of the pixels, whether the first pixel circuit or the second pixel circuit is to convert the electrical signal (pixel array 550 may include first unit pixels P1 10-1 and second unit pixels P2 10-2 arranged in rows and columns, where first unit pixels 10-1 and the second unit pixels 10-2 may have a same structure except that each of the first unit pixels 10-1 includes the first filter and each of the second unit pixels 10-2 includes the second filter and are implemented with the unit pixel 10 of FIG. 1, and where first unit pixels 10-1 and second unit pixels 10-2 operate the same as unit pixels 10, par. 167-175). Regarding claim 3, Kim further discloses: each of the plurality of pixels, switching between timing of output using the first pixel circuit (in the first operation mode control unit 850 provides an activated transmission control signal TX to the transmission transistor 311 of first signal generation unit 300b to turn on the transmission transistor 311, where the photo-charges accumulated in the first node N1 are transferred to the floating diffusion area FD through the transmission transistor 311, par. 75, 130, and Fig. 4) and timing of output using the second pixel circuit (in the second operation mode the first NMOS transistor 210 discharges the photo-charges generated from the photoelectric conversion unit 100 through the first NMOS transistor 210 to generate the sensing current IS, and the amplifier 220 generates the sensing voltage VS having a magnitude logarithmically proportional to the magnitude of the sensing current IS, par. 56, 59, 62-64, 84, 85, 101-107, 118, 122, and Figs. 2, 4-6 and 8). Regarding claim 4, Kim further discloses: a pixel array in which the plurality of pixels is arranged, wherein the plurality of pixels is arranged in a two-dimensional array along a line and a column extending in a direction intersecting a direction of the line in the pixel array (pixel array 500 may include a plurality of unit pixels P 10 arranged in rows and columns, par. 118 and Fig. 8). Regarding claim 5, Kim further discloses: control circuit performs, for each of regions in the pixel array, control for switching between the pixels that perform the output using the first pixel circuits and the pixels that perform the output using the second pixel circuits (pixel array 550 may include first unit pixels P1 10-1 and second unit pixels P2 10-2 arranged in rows and columns, where first unit pixels 10-1 and the second unit pixels 10-2 may have a same structure except that each of the first unit pixels 10-1 includes the first filter and each of the second unit pixels 10-2 includes the second filter and are implemented with the unit pixel 10 of FIG. 1, and where first unit pixels 10-1 and second unit pixels 10-2 operate the same as unit pixels 10, par. 167-175 and Fig. 11). Regarding claim 6, Kim further discloses: photoelectric conversion element is an element that obtains luminance information (photo-charges generated from the photoelectric conversion unit 100 may correspond to an intensity of incident light thereon, par. 53), the first pixel circuit converts the electrical signal into gradation information (in the first operation mode, each of the unit pixels 10 may generate the analog signal AS having a magnitude corresponding to an intensity of incident light, where first signal generation unit 300b may generate the analog signal AS in the first operation mode based on the amount of the photo-charges accumulated in the first node N1, par. 74-82, 119, 126, and Fig. 4), and the second pixel circuit converts the electrical signal into event detection information (in the second operation mode motion detection unit 700 may detect a motion of a subject based on the on signal ONS and the off signal OFFS provided from each of the unit pixels 10 to generate a direction signal DIRS representing a moving direction of the subject and a speed signal SPS representing a speed of the subject (considered motion/event detection information), par. 56, 59, 62-64, 84, 85, 101-107, 118, 122, and Figs. 2, 4-6 and 8). Regarding claim 8, Kim further discloses: control circuit switches, on a basis of time, between the first pixel circuits (in the first operation mode control unit 850 provides an activated transmission control signal TX to the transmission transistor 311 of first signal generation unit 300b to turn on the transmission transistor 311, where the photo-charges accumulated in the first node N1 are transferred to the floating diffusion area FD through the transmission transistor 311, par. 75, 130, and Fig. 4) and the second pixel circuits (in the second operation mode the first NMOS transistor 210 discharges the photo-charges generated from the photoelectric conversion unit 100 through the first NMOS transistor 210 to generate the sensing current IS, and the amplifier 220 generates the sensing voltage VS having a magnitude logarithmically proportional to the magnitude of the sensing current IS, par. 56, 59, 62-64, 84, 85, 101-107, 118, 122, and Figs. 2, 4-6 and 8). Regarding claim 9, Kim further discloses: control circuit switches between the first pixel circuits (in the first operation mode control unit 850 provides an activated transmission control signal TX to the transmission transistor 311 of first signal generation unit 300b to turn on the transmission transistor 311, where the photo-charges accumulated in the first node N1 are transferred to the floating diffusion area FD through the transmission transistor 311, par. 75, 130, and Fig. 4) and the second pixel circuits at periodic timing (in the second operation mode the first NMOS transistor 210 discharges the photo-charges generated from the photoelectric conversion unit 100 through the first NMOS transistor 210 to generate the sensing current IS, and the amplifier 220 generates the sensing voltage VS having a magnitude logarithmically proportional to the magnitude of the sensing current IS, where pixel array 500 may repeat above described operations such that the pixel array 500 may generate the analog signal AS row by row, par. 56, 59, 62-64, 84, 85, 101-107, 118, 122, 131, and Figs. 2, 4-6 and 8). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. Pub. No. 20140374572) in view of Kennedy et al. (U.S. Pub. No. 20210126025). Regarding claim 7, Kim is silent with regards to photoelectric conversion element is a single photon avalanche diode (SPAD),the first pixel circuit converts the electrical signal into photon counting information, and the second pixel circuit converts the electrical signal into information for obtaining time of flight (ToF) information. Kennedy discloses photoelectric conversion element is a single photon avalanche diode (SPAD) (SPADs 18, par. 108), the first pixel circuit converts the electrical signal into photon counting information (SPADs 18 facilitate photon counting suing photon counter 34 of front-end circuit 24, par. 108 and 11), and the second pixel circuit converts the electrical signal into information for obtaining time of flight (ToF) information (SPADs 18 facilitate the collection of time of flight information using timer 32 and photon counter 34 to implement time of flight determination, par. 108 and 111). As can be seen in par. 10 this is advantageous in that time of flight of a laser light pulse can be measured; the distance can thus be determined and the distance information used to determine a 3D distance profile of an irradiated object. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include photoelectric conversion element is a single photon avalanche diode (SPAD),the first pixel circuit converts the electrical signal into photon counting information, and the second pixel circuit converts the electrical signal into information for obtaining time of flight (ToF) information. Allowable Subject Matter Claims 10-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 10, no prior art could be located that teaches or fairly suggests control circuit performs control for spatially periodically arranging the pixels that use the first pixel circuits and the pixels that use the second pixel circuits in the pixel array, in combination with the rest of the limitations of the claim and parent claims. Claims 11-14 depend on claim 10 and therefore are objected to. Regarding claim 15, no prior art could be located that teaches or fairly suggests control circuit obtains event information based on the second signals in the pixel array, and determines, on a basis of the event information, timing of selecting whether each of the plurality of pixels is to be connected to the first pixel circuit or the second pixel circuit, in combination with the rest of the limitations of the claim and parent claims. Claims 16 and 17 depend on claim 15 and therefore are objected to. Regarding claim 18, no prior art could be located that teaches or fairly suggests control circuit obtains luminance information based on the first signals in the pixel array, and determines, on a basis of the luminance information, timing of selecting whether each of the plurality of pixels is to be connected to the first pixel circuit or the second pixel circuit, in combination with the rest of the limitations of the claim and parent claims. Claims 19 and 20 depend on claim 18 and therefore are objected to. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS G GILES whose telephone number is (571)272-2824. The examiner can normally be reached M-F 6:45AM-3:15PM EST (HOTELING). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at 571-272-7406. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS G GILES/ Primary Examiner, Art Unit 2639
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Prosecution Timeline

Dec 03, 2024
Application Filed
Mar 19, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
98%
With Interview (+16.5%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 834 resolved cases by this examiner. Grant probability derived from career allow rate.

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