Prosecution Insights
Last updated: April 19, 2026
Application No. 18/871,492

SOLID-STATE IMAGING ELEMENT AND IMAGING DEVICE

Non-Final OA §103
Filed
Dec 04, 2024
Examiner
SPINKS, ANTOINETTE T
Art Unit
2639
Tech Center
2600 — Communications
Assignee
Sony Semiconductor Solutions Corporation
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
92%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
654 granted / 913 resolved
+9.6% vs TC avg
Strong +20% interview lift
Without
With
+20.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
39 currently pending
Career history
952
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
49.0%
+9.0% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 913 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “photoelectric conversion unit”, “first electric charge holding unit”, “reset unit”, “counting unit”, “analog-digital conversion unit”, “signal processing unit”, “second electric charge holding unit” in claims. Because these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Funaki (US 2009/0244346) in view of Senda (US 2012/0049078). Regarding claim 1, Funaki discloses, in at least figures 1 – 3, a solid-state imaging element (CMOS) comprising: a photoelectric conversion unit (PD) that generates electric charges according to an amount of received light (¶54); a first electric charge holding unit (FD) that is connected to the photoelectric conversion unit via a first node (N1) (¶55); a comparator (CMP) that outputs a first signal when a potential of the first node and a predetermined potential (Vref) coincide with each other (¶58); a reset unit (Trst) that sets the first node to a reset potential (Vdd) according to the first signal (¶62); and a counting unit (CNT) that counts and outputs the first signal (¶63). Funaki fails to explicitly disclose wherein, in a first mode, the reset potential applied to the first node changes in time series. In a similar field of endeavor, Senda teaches a configuration of an imaging device wherein at the time of acquiring initial data Dorg and measurement data Dm to be described later, this voltage generation section 12 changes the value of the reset voltage Vrst stepwise within a voltage range that the storage node N may have during imaging (for example, in a range of 0 volt to the power source voltage SVDD); and by measuring the output voltage Vout (the signal voltage Vsig) from the source follower circuit while thus changing the reset voltage Vrst stepwise, the input-output characteristic of the source follower circuit is acquired (fig. 1, 3, 8; ¶38-44, 66). In light of the teaching of Senda, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to use Senda’s teaching in Funaki’s system because an artisan of ordinarily skill would recognize that this would result in the ability to accurately measure/monitor dark current. Regarding claim 2, Funaki in view of Senda disclose the limitations of claim 1. Funaki also teaches wherein, in a second mode, the reset potential having a fixed value is applied (¶62: Vdd is fixed). Regarding claim 3, Funaki in view of Senda disclose the limitations of claim 1. The combination also teaches wherein the reset unit includes a reset transistor (Trst) connected between the first node and a power supply unit (Funaki fig. 1), the comparator maintains an output of the first signal in a case where the potential of the first node exceeds the predetermined potential to a low potential side (Funaki ¶65: when potential of N1 is lower than Vref, CMP outputs a low-level potential), the reset unit causes the reset transistor to be in a conductive state during the output of the first signal (Funaki ¶65: as a result, Trst enters a conductive state), and, in the first mode, the potential of the power supply unit is so raised as to exceed the predetermined potential from the low potential side relative to the predetermined potential (Senda fig. 1, 3, 8; ¶38-44, 66: when measurement data is acquired, the value of the reset voltage is changed stepwise w/in a possible voltage range). Regarding claim 4, Funaki in view of Senda disclose the limitations of claim 3. Senda also teaches further comprising: a readout circuit that reads out the potential of the first node (fig. 3; ¶38:transistor 23 and 24). Claim(s) 13 rejected under 35 U.S.C. 103 as being unpatentable over Funaki (US 2009/0244346) in view of Senda (US 2012/0049078) in view of Miyauchi (US 2021/0099659). Regarding claim 3, Funaki in view of Senda disclose the limitations of claim 1. The combination fails to explicitly disclose an optical system. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Funaki with the teachings of Miyauchi. Miyauchi discloses a CMOS image sensor in an electronic apparatus that includes an optical system 220 (fig. 20; ¶182). One of ordinary skill in the art would have recognized that applying the known technique of using a lens/optical system, as taught by Miyauchi, with the invention of Funaki would have yielded predictable results and resulted in an improved system that allows for redirecting incident light. Allowable Subject Matter Claims 5 – 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Contact Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTOINETTE T. SPINKS whose telephone number is (571)270-3749. The examiner can normally be reached M-Th 7am - 5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at 571-272-7406. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTOINETTE T SPINKS/ Primary Examiner, Art Unit 2639
Read full office action

Prosecution Timeline

Dec 04, 2024
Application Filed
Feb 19, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
92%
With Interview (+20.4%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 913 resolved cases by this examiner. Grant probability derived from career allow rate.

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