DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to amendments and remarks filed July 29, 2026. Claim 1, 2 and 5-19 are currently pending.
Response to Arguments
Applicant’s arguments, see arguments and amendment, filed July 29, 2026, with respect to the rejection(s) of claim(s) 1, 18 and 19 under Miyamoto et al. (US 20190288150) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ota (US 20220357198).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 16, 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. (US 20190288150) in view of Ota (US 20220357198).
Re claim 1: Miyamoto teaches a light detecting device (fig. 1, 2, 10 and 11), comprising: a pixel (300n) comprising a light receiving element (301n) configured to receive light (paragraph 41, 42 and 103); and a pixel circuit (1002n/1001n/501n/208) comprising: a counter circuit (501n) configured to receive a first signal (PLSN in T1 and T2, fig. 11) based on an output of the light receiving element (301n) (fig. 10 and 11) and to output a second signal (output from 501n) based on a difference between a number of first signals in a first period (T1) and a number of first signals in a second period (T2) (paragraph 116, fig. 10 and 11); and a control circuit (1002n/1001n/208/207) configured to control the counter circuit (501n) (paragraphs 102-117, fig. 10 and 11), but does not specifically teach wherein the counter circuit is configured to output a detection signal when the number of first signals in the first period reaches a reference value; and wherein the detection signal indicates an end of the first period. Ota teaches wherein a counter circuit (16) is configured to output a detection signal when a number of first signals in a first period reaches a reference value (paragraph 65-72, first period is int1, which when counter meets reference/threshold a signal is output, to selector 13); and wherein the detection signal indicates an end of the first period (paragraph 65-72, first period is int1, which when counter meets reference/threshold a signal is output, to selector 13, and this is the end of int1 and beginning of int2, second period, fig. 3 and 5). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a reference value to end to indicate the end of the first period count similar to Ota with the circuit of Miyamoto in order to reduce the amount of power the pixel uses in high illuminance providing for a more efficient pixel design.
Re claim 2: Miyamoto as modified by Ota teaches the light detecting device, wherein the light receiving element (Miyamoto, 301n) includes a single photon avalanche diode (Miyamoto, paragraph 2, 42 and 103).
Re claim 5: Miyamoto as modified by Ota teaches the light detecting device, wherein the counter circuit includes an up-down counter (Miyamoto, 501n, paragraph 62).
Re claim 16: Miyamoto in figure 2 and 10 as modified by Ota teaches a plurality of the pixels (Miyamoto, 201, fig. 2), wherein a pixel (Miyamoto, 300n) comprising a light receiving element (Miyamoto, 301n) configured to receive light (Miyamoto, paragraph 41, 42 and 103); and a pixel circuit (Miyamoto, 1002n/1001n/501n/208) comprising: a counter circuit (Miyamoto, 501n) configured to receive a first signal (Miyamoto, PLSN in T1 and T2, fig. 11) based on an output of the light receiving element (Miyamoto, 301n) (Miyamoto, fig. 10 and 11) and to output a second signal (Miyamoto, output from 501n) based on a difference between a number of first signals in a first period (Miyamoto, T1) and a number of first signals in a second period (Miyamoto, T2) (Miyamoto, paragraph 116, fig. 10 and 11), but does not specifically teach a first substrate and a second substrate that are stacked with each other. Miyamoto in figure 14b teaches a first substrate (101a) including a plurality of a pixels (see fig. 14b); and a second substrate (101b) including a plurality of pixel circuits (fig. 14b), the first substrate (101a) being stacked on the second substrate (101b) (see fig. 14b). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the pixels on one substrate and the pixel circuitry on another substrate similar to figure 14 with the structure in figure 10 in order to reduce the size of the light detecting device providing for a compact design.
Re claim 17: Miyamoto in figure 2 and 10 as modified by Ota teaches a plurality of the pixels (Miyamoto, 201, fig. 2), wherein a pixel (Miyamoto, 300n) comprising a light receiving element (Miyamoto, 301n) configured to receive light (Miyamoto, paragraph 41, 42 and 103); and a pixel circuit (Miyamoto, 1002n/1001n/501n/208/207), comprising: a counter circuit (Miyamoto, 501n) configured to receive a first signal (Miyamoto, PLSN in T1 and T2, fig. 11) based on an output of the light receiving element (Miyamoto, 301n) (Miyamoto, fig. 10 and 11) and to output a second signal (Miyamoto, output from 501n) based on a difference between a number of first signals in a first period (Miyamoto, T1) and a number of first signals in a second period (Miyamoto, T2) (Miyamoto, paragraph 116, fig. 10 and 11), but does not specifically teach the pixel circuit is directly below the pixel. Miyamoto in figure 14b teaches a first substrate (101a) including a plurality of a pixels (see fig. 14b); and a second substrate (101b) including a plurality of pixel circuits (fig. 14b), the first substrate (101a) being stacked on the second substrate (101b) (see fig. 14b), where the pixel circuit is directly below the pixel (see fig. 14b). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the pixels on one substrate and the pixel circuitry on another substrate similar to figure 14 with the structure in figure 10 in order to reduce the size of the light detecting device providing for a compact design.
Re claim 19: Miyamoto teaches an electronic apparatus (fig. 1, 2, 10 and 11), comprising: a signal processor (103); and a light detecting device (101), comprising: a pixel (300n) comprising a light receiving element (301n) configured to receive light (paragraph 41, 42 and 103); and a pixel circuit (1002n/1001n/501n/208) comprising: a counter circuit (501n) configured to receive a first signal (PLSN in T1 and T2, fig. 11) based on an output of the light receiving element (301n) (fig. 10 and 11) and to output a second signal (output from 501n) based on a difference between a number of first signals in a first period (T1) and a number of first signals in a second period (T2) (paragraph 116, fig. 10 and 11); and a control circuit (1002n/1001n/208/207) configured to control the counter circuit (501n) (paragraphs 102-117, fig. 10 and 11), but does not specifically teach wherein the counter circuit is configured to output a detection signal when a number of first signals in a first period reaches a reference value; and wherein the detection signal indicates an end of the first period. Ota teaches wherein a counter circuit (16) is configured to output a detection signal when a number of first signals in a first period reaches a reference value (paragraph 65-72, first period is int1, which when counter meets reference/threshold a signal is output, to selector 13); and wherein the detection signal indicates an end of the first period (paragraph 65-72, first period is int1, which when counter meets reference/threshold a signal is output, to selector 13, and this is the end of int1 and beginning of int2, second period, fig. 3 and 5). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a reference value to end to indicate the end of the first period count similar to Ota with the circuit of Miyamoto in order to reduce the amount of power the pixel uses in high illuminance providing for a more efficient pixel design.
Claim(s) 6, 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. (US 20190288150) as modified by Ota (US 20220357198) as applied to claim 1 above, and further in view of Inaoka et al. (US 20200382726).
Re claim 6: Miyamoto as modified by Ota teaches wherein a counter circuit (Ota, 16) is configured to output a detection signal when a number of first signals in a first period reaches a reference value (Ota, paragraph 65-72, first period is int1, which when counter meets reference/threshold a signal is output, to selector 13); and wherein the detection signal indicates an end of the first period (Ota, paragraph 65-72, first period is int1, which when counter meets reference/threshold a signal is output, to selector 13, and this is the end of int1 and beginning of int2, second period, fig. 3 and 5), wherein the control circuit is configured to control the photodiode based on the detection signal (fig. 3), but does not specifically teach wherein the control circuit is configured to control the counter circuit based on the detection signal. Inaoka teaches wherein a control circuit is configured to control the counter circuit based on the detection signal (fig. 14, paragraphs 120-129). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to control the counter circuit based on the detection signal similar to Inaoka with the control circuit of Miyamoto as modified by Ota in order to control the counter directly by starting or stopping a count providing for more accurate control of the pixel with reduced power consumption.
Re claim 7: Miyamoto as modified by Ota teaches wherein a counter circuit (Ota, 16) is configured to output a detection signal when a number of first signals in a first period reaches a reference value (Ota, paragraph 65-72, first period is int1, which when counter meets reference/threshold a signal is output, to selector 13); and wherein the detection signal indicates an end of the first period (Ota, paragraph 65-72, first period is int1, which when counter meets reference/threshold a signal is output, to selector 13, and this is the end of int1 and beginning of int2, second period, fig. 3 and 5), wherein the control circuit is configured to control the photodiode based on the detection signal (fig. 3), but does not specifically teach wherein the control circuit is configured to output a stop signal indicating an end of the second period to the counter circuit based on the detection signal. Inaoka teaches wherein a control circuit is configured to output a stop signal indicating an end of the second period to the counter circuit based on the detection signal (fig. 14, paragraphs 13 and 120-129). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to control the counter circuit based on the detection signal similar to Inaoka with the control circuit of Miyamoto as modified by Ota in order to control the counter directly by starting or stopping a count providing for more accurate control of the pixel with reduced power consumption.
Re claim 9: Miyamoto as modified by Ota and Inaoka teaches the light detecting device, wherein the control circuit (Miyamoto, 1002n/1001n/208/207) includes a timing generator (Miyamoto, 207, paragraph 39).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. (US 20190288150) as modified by Ota (US 20220357198) as applied to claim 1 above, and further in view of Drader et al. (US 20170139041).
Re claim 10: Miyamoto as modified by Ota teaches the counter circuit (501n) configured to receive a first signal (Miyamoto, PLSN in T1 and T2, fig. 11) based on an output of the light receiving element (Miyamoto, 301n) (Miyamoto, fig. 10 and 11) and to output a second signal (Miyamoto, output from 501n) based on a difference between a number of first signals in a first period (Miyamoto, T1) and a number of first signals in a second period (Miyamoto, T2) (Miyamoto, paragraph 116, fig. 10 and 11), but does not specifically teach further comprising a signal processing circuit configured to generate a third signal based on a sum of the number of first signals in the first period and the number of first signals in the second period. Drader teaches a signal processing circuit (216/218) configured to generate a third signal based on a sum of a number of first signals in a first period and a number of first signals in a second period (paragraphs 45 47). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include processing circuitry similar to Drader with the circuitry of Miyamoto as modified by Ota in order to use the detected light within specific periods of time to form a specific measurement providing for a versatile design.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. (US 20190288150) as modified by Ota (US 20220357198) and Drader et al. (US 20170139041) as applied to claim 10 above, and further in view of Suzuki et al. (US 20200358972).
Re claim 12: Miyamoto as modified by Ota and Drader teaches a signal processing circuit (Drader, 216/218) configured to generate a third signal based on a sum of a number of first signals in a first period and a number of first signals in a second period (Drader, paragraphs 45-47, Miyamoto, fig. 10), but does not specifically teach wherein the signal processing circuit includes a memory configured to hold the third signal. Suzuki teaches wherein a signal processing circuit (paragraph 48) includes a memory configured to hold the third signal (paragraph 48, fig. 3). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a memory with the signal processing circuit of Miyamoto as modified by Ota and Drader similar to Suzuki in order to store outputs as desired providing for a versatile design.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. (US 20190288150) as modified by Ota (US 20220357198) as applied to claim above, and further in view of Koizumi et al. (US 20200045251).
Re claim 14: Miyamoto as modified by Ota teaches the light detecting device, further comprising a plurality of the pixels (Miyamoto, 201, fig. 2), but does not specifically teach wherein the plurality of the pixels includes at least one of a pixel including the light receiving element configured to receive visible light and a pixel including the light receiving element configured to receive non-visible light. Koizumi teaches wherein a plurality of the pixels includes at least one of a pixel including the light receiving element configured to receive visible light and a pixel including the light receiving element configured to receive non-visible light (paragraph 36). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include an infrared and a visible pixel in the plurality of pixels of Miyamoto as modified by Ota similar to Koizumi in order to capture color images and infrared images in the same light detection device providing for a more versatile design.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. (US 20190288150) as modified by Ota (US 20220357198) as applied to claim 1 above, and further in view of Morimoto (US 20230258776).
Re claim 15: Miyamoto as modified by Ota teaches the counter circuit (Miyamoto, 501n) configured to receive a first signal (Miyamoto, PLSN in T1 and T2, fig. 11) based on an output of the light receiving element (Miyamoto, 301n) (Miyamoto, fig. 10 and 11) and to output a second signal (Miyamoto, output from 501n) based on a difference between a number of first signals in a first period (Miyamoto, T1) and a number of first signals in a second period (Miyamoto, T2) (Miyamoto, paragraph 116, fig. 10 and 11), but does not specifically teach wherein the counter circuit includes a first counter and a second counter each configured to count the first signal, the first counter is configured to count the number of first signals in the first period, and the second counter is configured to count the number of first signals in the second period. Morimoto teaches wherein a counter circuit (310a/310b) includes a first counter (310a) and a second counter (310b) each configured to count a first signal, the first counter (310a) is configured to count the number of first signals in the first period (paragraph 72), and the second counter (310b) is configured to count the number of first signals in the second period (paragraph 72, fig. 5 and 6). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the counter circuit of Miyamoto as modified by Ota include a first and second counter similar to Morimoto in order to count the first pulses during different time periods in parallel with separate counters providing increased processing speeds (Morimoto, paragraph 74).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. (US 20190288150) in view of Ota (US 20220357198) and Dargan (US 20120133617).
Re claim 18: Miyamoto teaches a light detecting device (fig. 1, 2, 10 and 11), comprising: a pixel comprising a light receiving element (301n) (see fig. 10); and a pixel circuit (1002n/1001n/501n/208/207) (fig. 2 and 10) comprising a counter circuit (501n) and a control circuit (1002n/1001n/208/207), wherein the light detecting device is configured to detect a motion signal (paragraph 102-116) and a control circuit (1002n/1001n/208/207) configured to control the counter circuit (501n) (paragraphs 102-117, fig. 10 and 11), but does not specifically teach a separate detection of an intensity signal and wherein the counter circuit is configured to output a detection signal when the number of first signals in the first period reaches a reference value; and wherein the detection signal indicates an end of the first period. Ota teaches wherein a counter circuit (16) is configured to output a detection signal when a number of first signals in a first period reaches a reference value (paragraph 65-72, first period is int1, which when counter meets reference/threshold a signal is output, to selector 13); and wherein the detection signal indicates an end of the first period (paragraph 65-72, first period is int1, which when counter meets reference/threshold a signal is output, to selector 13, and this is the end of int1 and beginning of int2, second period, fig. 3 and 5). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a reference value to end to indicate the end of the first period count similar to Ota with the circuit of Miyamoto in order to reduce the amount of power the pixel uses in high illuminance providing for a more efficient pixel design. Miyamoto as modified by Ota does not specifically teach a separate detection of an intensity signal. Dargan teaches wherein a light detecting device (fig. 2 and 3, light receiver, counter) is configured to detect an intensity signal and a motion signal (paragraphs 22-33, 39 and 40). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the light detection device of Miyamoto as modified by Ota detect intensity and motion similar to Dargan in order to compensate for background illumination providing for higher quality light detection.
Allowable Subject Matter
Claims 8, 11 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regards to claim 8, the prior art of record individually or in combination fails to teach the light detecting device according to claims 7 and 1 as claimed, more specifically in combination with wherein the control circuit is configured to output the stop signal indicating the end of the second period to the counter circuit to substantially equalize respective lengths of the first period and the second period.
In regards to claim 11, the prior art of record individually or in combination fails to teach the light detecting device according to claims 10 and 1 as claimed, more specifically in combination with wherein the signal processing circuit includes a bit inversion circuit configured to invert a bit value of the second signal to generate the third signal.
In regards to claim 13, the prior art of record individually or in combination fails to teach the light detecting device according to claims 10 and 1 as claimed, more specifically in combination with wherein the signal processing circuit is configured to average a plurality of the third signals in accordance with the difference between the number of first signals in the first period and the number of first signals in the second period and output the averaged third signal.
Conclusion
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/JENNIFER D BENNETT/Examiner, Art Unit 2878
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