DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 & 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Abdoli (EP-3962080-A1) in view of Sidar et al., hereinafter referred to as Sidar (US 2016/0335751 A1).
As per claim 1, Abdoli discloses a video coding method (Abdoli: Abstract.) comprising:
receiving data for a block of pixels to be encoded or decoded as a current block of a current picture of a video (Abdoli: Para. [0052] discloses “a video encoder 100 that receives at input 109 an input video stream 101 that includes a plurality of images [claimed current picture of a video]”; Abdoli: Para. [0056] discloses “One may therefore consider a so-called “current block,” that is, a block being under processing in the current image [claimed receiving data for a block of pixels to be encoded as a current block]”.);
deriving a histogram of gradients (HoG) comprising a plurality of bins corresponding to different intra prediction angles, wherein a value for an accumulated gradient amplitude of each bin is stored and (Abdoli: Para. [0339] discloses “Histogram of Gradient (HoG) [claimed deriving a histogram of gradients (HoG)] … histogram … with 65 entries [claimed comprising a plurality of bins], corresponding to the set of angular [claimed corresponding to different intra prediction angles] IPMs” and Abdoli: Para. [0347] discloses “the HoG can be updated with the gradient intensity [claimed wherein a value for an accumulated gradient amplitude of each bin is stored]”.);
identifying two or more intra prediction modes based on the HoG (Abdoli: Para. [0289] discloses “NDIMD intra prediction modes are selected [claimed identifying two or more intra prediction modes] based on the NDIMD largest HoG values [claimed based on the HoG]”.);
generating an intra-prediction of the current block based on the identified two or more intra prediction modes (Abdoli: Para. [0289] discloses “NDIMD predictors Pi (i = 1... NDIMD) are then computed using the NDIMD selected intra prediction video coding modes. The final predictor PB is computed [claimed generating an intra-prediction of the current block] as a pixel to pixel average of predictors Pi [claimed based on the identified two or more intra prediction modes]”.); and
encoding or decoding the current block by using the generated intra-prediction (Abdoli: Para. [0110] discloses “The current pixel block may then be processed that is, for example, encoded at the encoder side, or decoded at the decoder side [claimed encoding or decoding the current block], according to the generated final block predictor [claimed by using the generated intra-prediction]”.).
However, Abdoli does not explicitly disclose “… the value is constrained by a particular bit-width …”.
Further, Sidar is in the same field of endeavor and teaches the value is constrained by a particular bit-width (Sidar: Para. [0103] discloses “each histogram is based on one FPGA-internal 9K-bit memory module providing 512 bins of 18 bit each [claimed the value is constrained by a particular bit-width]”.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, and having the teachings of Abdoli and Sidar before him or her, to modify the histogram entries of Abdoli to include the histogram bins constrained bit-width feature as described in Sidar. The motivation for doing so would have been to improve hardware utilization, reduced logic costs, and enable efficient real-time processing by providing a configuration that efficiently maps histogram bins into standard memory modules.
As per claim 2, Abdoli-Sidar disclose the video coding method of claim 1, wherein the particular bit-width is 18 bits (Sidar: Para. [0103] discloses “providing 512 bins of 18 bit each [claimed wherein the particular bit-width is 18 bits]”.).
As per claim 3, Abdoli-Sidar disclose the video coding method of claim 1, wherein the particular bit-width is one of 12, 13, 14, 15, 16, 17, 18, 19, and 20 bits (Sidar: Para. [0103] discloses “providing 512 bins of 18 bit each [claimed wherein the particular bit-width is 18 bits]”.).
As per claim 11, Abdoli discloses an electronic apparatus (Abdoli: Abstract.) comprising:
a video coder circuit configured to perform operations comprising (Abdoli: Para. [0319] discloses “video coding and/or decoding apparatus [claimed video coder circuit] or unit 1 configured to use an image processing feature”; Para. [0322] discloses “the image processing engine 3 may be configured to perform various aspects of embodiments of the proposed method for image processing as described herein [claimed configured to perform operations comprising]”.):
receiving data for a block of pixels to be encoded or decoded as a current block of a current picture of a video (Abdoli: Para. [0052] discloses “a video encoder 100 that receives at input 109 an input video stream 101 that includes a plurality of images [claimed current picture of a video]”; Abdoli: Para. [0056] discloses “One may therefore consider a so-called “current block,” that is, a block being under processing in the current image [claimed receiving data for a block of pixels to be encoded as a current block]”.);
deriving a histogram of gradients (HoG) comprising a plurality of bins corresponding to different intra prediction angles, wherein a value for an accumulated gradient amplitude of each bin is stored and (Abdoli: Para. [0339] discloses “Histogram of Gradient (HoG) [claimed deriving a histogram of gradients (HoG)] … histogram … with 65 entries [claimed comprising a plurality of bins], corresponding to the set of angular [claimed corresponding to different intra prediction angles] IPMs” and Abdoli: Para. [0347] discloses “the HoG can be updated with the gradient intensity [claimed wherein a value for an accumulated gradient amplitude of each bin is stored]”.);
identifying two or more intra prediction modes based on the HoG (Abdoli: Para. [0289] discloses “NDIMD intra prediction modes are selected [claimed identifying two or more intra prediction modes] based on the NDIMD largest HoG values [claimed based on the HoG]”.);
generating an intra-prediction of the current block based on the identified two or more intra prediction modes (Abdoli: Para. [0289] discloses “NDIMD predictors Pi (i = 1... NDIMD) are then computed using the NDIMD selected intra prediction video coding modes. The final predictor PB is computed [claimed generating an intra-prediction of the current block] as a pixel to pixel average of predictors Pi [claimed based on the identified two or more intra prediction modes]”.); and
encoding or decoding the current block by using the generated intra-prediction (Abdoli: Para. [0110] discloses “The current pixel block may then be processed that is, for example, encoded at the encoder side, or decoded at the decoder side [claimed encoding or decoding the current block], according to the generated final block predictor [claimed by using the generated intra-prediction]”.).
However, Abdoli does not explicitly disclose “… the value is constrained by a particular bit-width …”.
Further, Sidar is in the same field of endeavor and teaches the value is constrained by a particular bit-width (Sidar: Para. [0103] discloses “each histogram is based on one FPGA-internal 9K-bit memory module providing 512 bins of 18 bit each [claimed the value is constrained by a particular bit-width]”.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, and having the teachings of Abdoli and Sidar before him or her, to modify the histogram entries of Abdoli to include the histogram bins constrained bit-width feature as described in Sidar. The motivation for doing so would have been to improve hardware utilization, reduced logic costs, and enable efficient real-time processing by providing a configuration that efficiently maps histogram bins into standard memory modules.
As per claim 12, Abdoli discloses a video decoding method (Abdoli: Abstract.) comprising:
receiving data for a block of pixels to be decoded as a current block of a current picture of a video (Abdoli: Para. [0323] discloses “receive an encoded bit stream and output decoded video data [claimed receiving data for a block of pixels to be decoded]”; Para. [0085] discloses “decoding of an image divided into a plurality of pixel blocks … sequentially decoding the pixel blocks according to a processing sequence to determine for a current pixel block [claimed as a current block of a current picture of a video]”.);
deriving a histogram of gradients (HoG) comprising a plurality of bins corresponding to different intra prediction angles, wherein a value for an accumulated gradient amplitude for each bin is stored (Abdoli: Para. [0339] discloses “Histogram of Gradient (HoG) [claimed deriving a histogram of gradients (HoG)] … histogram … with 65 entries [claimed comprising a plurality of bins], corresponding to the set of angular [claimed corresponding to different intra prediction angles] IPMs” and Abdoli: Para. [0347] discloses “the HoG can be updated with the gradient intensity [claimed wherein a value for an accumulated gradient amplitude of each bin is stored]”.);
identifying two or more intra prediction modes based on the HoG (Abdoli: Para. [0289] discloses “NDIMD intra prediction modes are selected [claimed identifying two or more intra prediction modes] based on the NDIMD largest HoG values [claimed based on the HoG]”.);
generating an intra-prediction of the current block based on the identified two or more intra prediction modes (Abdoli: Para. [0289] discloses “NDIMD predictors Pi (i = 1... NDIMD) are then computed using the NDIMD selected intra prediction video coding modes. The final predictor PB is computed [claimed generating an intra-prediction of the current block] as a pixel to pixel average of predictors Pi [claimed based on the identified two or more intra prediction modes]”.); and
reconstructing the current block by using the generated intra-prediction (Abdoli: Para. [0110] discloses “The current pixel block may then be processed that is, for example … decoded at the decoder side, according to the generated final block predictor [claimed reconstructing the current block by using the generated intra-prediction]”.).
However, Abdoli does not explicitly disclose “… the value is constrained by a particular bit-width …”.
Further, Sidar is in the same field of endeavor and teaches the value is constrained by a particular bit-width (Sidar: Para. [0103] discloses “each histogram is based on one FPGA-internal 9K-bit memory module providing 512 bins of 18 bit each [claimed the value is constrained by a particular bit-width]”.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, and having the teachings of Abdoli and Sidar before him or her, to modify the histogram entries of Abdoli to include the histogram bins constrained bit-width feature as described in Sidar. The motivation for doing so would have been to improve hardware utilization, reduced logic costs, and enable efficient real-time processing by providing a configuration that efficiently maps histogram bins into standard memory modules.
As per claim 13, the claim(s) recites analogous limitations to claim(s) 1, 11-12 above, and is/are therefore rejected on the same premise.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Abdoli in view of Sidar in further view of Mimar (US 7,873,812 B1).
As per claim 4, Abdoli-Sidar disclose the video coding method of claim 1, wherein the stored accumulated gradient amplitude is clamped to be less than a particular value (Sidar: Para. [0104] discloses “The bins may be clipped beyond the set threshold level”.).
However, Abdoli-Sidar do not explicitly disclose “… based on the particular bit-width.”.
Further, Mimar is in the same field of endeavor and teaches clamping less than a particular value “based on the particular bit-width” (Mimar: Col 9, ll. 51-54 disclose “where each vector element of vector register is 16-bits, and vector accumulator elements are 48-bits each, it is necessary to perform clamping” and Mimar: claim 10 discloses “wherein values stored in elements of said vector accumulator [accumulated gradient amplitude] is clamped to a range of numbers represented by the number of bits” [claimed is clamped to be less than a particular value based on the particular bit-width].).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, and having the teachings of Abdoli-Sidar and Mimar before him or her, to modify the histogram accumulator of Abdoli-Sidar to include the bit-width based clamping limit feature as described in Mimar. The motivation for doing so would have been to improve safe accumulation and maintaining computational accuracy by providing a configuration that utilizes saturated arithmetic techniques.
Claims 5 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over Abdoli in view of Sidar in further view of Farmahini-Farahani et al., hereinafter referred to as Farahani (“Modular Design of High-Throughput, Low-Latency Sorting Units”; IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 7, JULY 2013; URL: https://afarmahini.github.io/tc12.pdf).
As per claim 5, Abdoli-Sidar disclose the video coding method of claim 1, wherein the two or more intra prediction modes are identified from the plurality of bins of the HoG [by analysis] (Abdoli: Para. [0271] discloses “two intra prediction video coding modes are to be selected based on the gradient analysis, such intra prediction video coding modes [claimed identifying two or more intra prediction modes] may be selected based on the histogram of gradient [claimed from the plurality of bins of the HoG]” and Sidar: Para. [0103] discloses “providing 512 bins of 18 bit each”.).
However, Abdoli-Sidar do not explicitly disclose “… by a comparator structure comprising one or more N-in-M-out comparator elements, wherein each N-in-M-out element selects M largest values from N values, wherein M is an integer greater or equal to two and N is an integer larger than M.”.
Further, Farahani is in the same field of endeavor and teaches by a comparator structure comprising one or more N-in-M-out comparator elements, wherein each N-in-M-out element selects M largest values from N values, wherein M is an integer greater or equal to two and N is an integer larger than M (Farahani: Abstract discloses “The sorting units [claimed a comparator structure] are optimized for situations in which only the M largest numbers from N inputs are needed [claimed comprising one or more N-in-M-out comparator elements, wherein each N-in-M-out element selects M largest values from N values]” and Farahani: Section 1, Col. 2 disclose “partial sorting and max-set-selection units that return the M=2m [claimed M is an integer greater or equal to two] largest values from N=2n inputs, where m and n are each whole numbers and 1≤M<N [claimed and N is an integer larger than M]”.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, and having the teachings of Abdoli-Sidar and Farahani before him or her, to modify the selection logic of Abdoli-Sidar to include the N-in-M-out comparator elements feature as described in Farahani. The motivation for doing so would have been to improve high-throughput optimization and low-latency selection performance by providing a configuration that simplifies the design process and reduces verification time.
As per claim 8, Abdoli-Sidar disclose the video coding method of claim 5, wherein at least an input or at least an output of the N-in-M-out comparator element is constrained by the particular bit-width (Sidar: Para. [0103] discloses the constrained by the particular bit-width and Farahani: Section 4, Page 1396 disclose “the parameterizable data width (i.e, the CAE width) [claimed at least an input or at least an output of the N-in-M-out comparator element], which can be easily changed, is set to 10 unsigned bits [claimed is constrained by the particular bit-width]”).
Allowable Subject Matter
Claims 6-7, 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and can be viewed in the list of references.
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/PEET DHILLON/Primary Examiner
Art Unit: 2488
Date: 07-05-2026
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