Prosecution Insights
Last updated: October 02, 2026
Application No. 18/871,999

IMAGE SENSOR AND METHOD FOR DRIVING THE SAME

Non-Final OA §102
Filed
Dec 05, 2024
Priority
Jun 08, 2022 — JP 2022-092846 +1 more
Examiner
HODGES, SUSAN E
Art Unit
2425
Tech Center
2400 — Computer Networks
Assignee
Tohoku University
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
261 granted / 389 resolved
+9.1% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
22 currently pending
Career history
423
Total Applications
across all art units

Statute-Specific Performance

§101
6.3%
-33.7% vs TC avg
§103
49.6%
+9.6% vs TC avg
§102
18.8%
-21.2% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 389 resolved cases

Office Action

§102
DETAILED ACTION This office action is in response to the application filed on December 5, 2024. Claims 1 – 9 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP2022-092846, filed on June 3, 2022. Information Disclosure Statement The information disclosure statement (IDS) was submitted on December 5, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 - 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TANAKA HIROMASA (JP 2021148745 A) (See IDS filed on December 5, 2024) referred to as HIROMASA hereinafter. Regarding Claim 1, HIROMASA discloses an image sensor (Fig. 3configuration of the pixels of the light receiving sensor 11), comprising: a light reception element configured to receive incident light (Page 6, one pixel of the light receiving sensor 11 has a PD (photodiode) 103); a plurality of voltage signal generation circuitries configured to acquire charge of the light reception element at a plurality of charge acquisition timings (Page 5, Each pixel performs a charge accumulation operation according to the timing signal A and the timing signal B from the timing control unit 12) and convert the charge into a plurality of voltage signals (Page 5, When the light receiving data output instruction signal is input from the timing control unit 12, the light receiving sensor 11 converts the amount of charge stored in the storage unit A and the storage unit B of each pixel into a voltage (i.e. voltage signal generation), and converts the light receiving signal A and the light receiving signal B into a voltage (i.e. plurality of voltage signals)); a pixel output circuitry configured to output a plurality of detected voltages based on the plurality of voltage signals (Page 5, The light receiving signal A and the light receiving signal B are AD-converted to generate the light receiving data A and the light receiving data B. The light receiving sensor 11 sequentially outputs the light receiving data A and the light receiving data B to the distance calculation unit 13. The distance calculation unit 13 calculates the distance data in each pixel using the light receiving data A and the light receiving data B in response to the distance calculation instruction signal, and generates a distance image); and a plurality of pixel memories configured to integrally store the plurality of detected voltages related to the plurality of charge acquisition timings in a plurality of memory cells, wherein the pixel output circuitry reads and outputs the detected voltages stored in the plurality of memory cells (Fig. 12, Page 9-11, In the distance measuring device 1, the phase signal is sequentially read from the light receiving sensor 11 to the distance calculation unit 13 for each light emitting pulse group, and the signal value is stored in the memories 1311 to 1315 (i.e. plurality of pixel memories). Each distance measurement calculation unit 1321 to 1325 calculates each distance from the signal value of the phase signal stored in the corresponding memories 1311 to 1315 (i.e. read and outputs)). Regarding Claim 2, HIROMASA discloses claim 1. HIROMASA further discloses wherein the plurality of memory cells correspond to a plurality of storage periods including the plurality of charge acquisition timings, and each integrally store the plurality of detected voltages in a corresponding one of the storage periods (Page 9, In the distance measuring device 1, the phase signal is sequentially read from the light receiving sensor 11 to the distance calculation unit 13 for each light emitting pulse group, and the signal value is stored in the memories 1311 to 1315. For example, the signal value of the phase signal of the storage period 0-180_P1 is stored in the P1 signal memory 1311, the signal value of the phase signal of the storage period 0-180_P2 is stored in the P2 signal memory 1312, ... The signal value of the phase signal of is stored in the P5 signal memory 1315). Regarding Claim 3, HIROMASA discloses claim 1. HIROMASA further discloses wherein the pixel output circuitry averages and reads the detected voltages stored in the plurality of memory cells (Fig. 12, page 9, the average calculation unit 1326 calculates the average distance of each calculated distance obtained from each pulse group, and outputs the result as a distance image). Regarding Claim 4, HIROMASA discloses claim 1. HIROMASA further discloses wherein the pixel output circuitry individually reads the detected voltages stored in the plurality of memory cells (Fig. 12, page 9, the phase signal is sequentially read (i.e. individually) from the light receiving sensor 11 to the distance calculation unit 13 for each light emitting pulse group, and the signal value is stored in the memories 1311 to 1315). Regarding Claim 5, HIROMASA discloses claim 1. HIROMASA further discloses wherein each of the plurality of pixel memories acquire the voltage signals corresponding to different phase sections in a cycle of the plurality of charge acquisition timings, and store the detected voltage for each of the phase sections (Page 9, the signal value of the phase signal of the storage period 0-180_P1 is stored in the P1 signal memory 1311, the signal value of the phase signal of the storage period 0-180_P2 is stored in the P2 signal memory 1312, ... The signal value of the phase signal of is stored in the P5 signal memory 1315). Regarding Claim 6, HIROMASA discloses claim 3. HIROMASA further discloses wherein number of the voltage signal generation circuitries provided is four (Page 5, The TOF type light receiving sensor 11 has a pixel structure in which electric charges are distributed to two places for each pixel. This pixel structure is for, for example, to make it possible to distribute a signal to a phase component of 0 ° and a phase component of 180 ° during a light receiving period of 1 degree. In principle, it is possible to have a pixel structure that distributes each pixel to three or more locations, and to distribute to three or more phase components with one light reception, but if the number of distribution locations is increased, the charge in the pixel area will be charged.). Regarding Claim 7, HIROMASA discloses claim 5. HIROMASA further discloses wherein number of the voltage signal generation circuitries provided is two (i.e. TX1 and TX2), and number of the phase sections is four (Fig. 4, pages 6-7, in the first half of the subframe period, the pixel modulation switches 104a and 104b are alternately turned on a predetermined number of times by the transfer signal TX1 (0 °) and the transfer signal TX2 (180 °) deviated by 180 ° from the transfer signal TX1 (0 °). .sub.After that, a signal (A 0 , A .sub.180 ) corresponding to the phase of 0 ° and 180 ° in time and corresponding to the accumulated charge amount is read and acquired by the “read out” signal. In the latter subframe period, the pixel modulation switches 104a and 104b are alternately turned on a predetermined number of times by the transfer signal TX1 (90 °) and the transfer signal TX2 (270 °) deviated by 180 ° from the transfer signal TX1 (90 °). .sub.After that, a signal (A 90 , A .sub.270 ) corresponding to the phase of 90 ° and 270 ° in time and corresponding to the accumulated charge amount is read and acquired by the “read out” signal (i.e. 0 °, 90 °, 180 ° and 270 ° are four phase sections)). Regarding Claim 8, HIROMASA discloses claim 1. HIROMASA further discloses wherein the incident light is reflected light of light source pulsed light (Fig. 1, page 4, The light projecting unit 10 emits pulsed light toward the object 2 to be measured) of a predetermined cycle (Page 5, the timing control unit 12 repeatedly generates a pulse of the modulated signal (i.e. predetermined cycle) and outputs it to the light projecting unit 10. When the modulation signal shown in FIG. 2 is supplied from the timing control unit 12 to the light projecting unit 10, the light projecting unit 10 irradiates the irradiation light Le (i.e. predetermined cycle) toward the measurement object 2.). Regarding Claim 9, HIROMASA discloses a method of driving an image sensor (Page 4, the distance measuring device 1 can be configured as shown in FIG. FIG. 1 is a diagram showing a schematic configuration of a distance measuring device 1. The distance measuring device 1 measures the distance to the object 2 to be measured by using the TOF method) configured to receive incident light by a light reception element (Page 6, one pixel of the light receiving sensor 11 has a PD (photodiode) 103), acquire charge of the light reception element at a plurality of charge acquisition timings (Page 5, Each pixel performs a charge accumulation operation according to the timing signal A and the timing signal B from the timing control unit 12) and convert the charge into a plurality of voltage signals (Page 5, When the light receiving data output instruction signal is input from the timing control unit 12, the light receiving sensor 11 converts the amount of charge stored in the storage unit A and the storage unit B of each pixel into a voltage (i.e. voltage signal generation), and converts the light receiving signal A and the light receiving signal B into a voltage (i.e. plurality of voltage signals)), and output a plurality of detected voltages based on the plurality of voltage signals from a pixel (Page 5, The light receiving signal A and the light receiving signal B are AD-converted to generate the light receiving data A and the light receiving data B. The light receiving sensor 11 sequentially outputs the light receiving data A and the light receiving data B to the distance calculation unit 13. The distance calculation unit 13 calculates the distance data in each pixel using the light receiving data A and the light receiving data B in response to the distance calculation instruction signal, and generates a distance image), the method comprising: integrally storing the plurality of detected voltages related to the plurality of charge acquisition timings in a plurality of memory cells (Fig. 12, Page 9, The memory group 131 has a number of memories (i.e. plurality of memory cells) corresponding to the number of divisions of the storage period in the drive method. In the distance measuring device 1, the phase signal is sequentially read from the light receiving sensor 11 to the distance calculation unit 13 for each light emitting pulse group, and the signal value is stored in the memories 1311 to 1315 (i.e. plurality of pixel memories). For example, the signal value of the phase signal of the storage period 0-180_P1 is stored in the P1 signal memory 1311, the signal value of the phase signal of the storage period 0-180_P2 is stored in the P2 signal memory 1312, ... The signal value of the phase signal of is stored in the P5 signal memory 1315); and reading and outputting the detected voltages stored in the plurality of memory cells (Page 11, In the distance measuring device 1, the phase signal is sequentially read from the light receiving sensor 11 to the distance calculation unit 13 for each light emitting pulse group, and the signal value is stored in the memories 1311 to 1315. The plurality of memories 1311 to 1315 in the memory group 131 and the plurality of distance measuring calculation units 1321 to 1325 in the calculation unit 132 correspond to each other (i.e. reading and outputting). In the calculation unit 132, each distance measurement calculation unit 1321 to 1325 calculates each distance from the signal value of the phase signal stored in the corresponding memories 1311 to 1315). Conclusion The prior art references made of record are not relied upon but are considered pertinent to applicant's disclosure. Kang et al. (US 9,628,774 B2) teaches an apparatus and method for correcting a depth error generated by saturation during the obtaining of a depth image from a time of flight (TOF) depth sensor. Choi et al. (US 11,467,264 B2) teaches an apparatus and method for measuring depth with pseudo 4-tap pixel structure. SCHAALE et al. (US 2022/0075064 A1) teaches a time of flight (TOF) camera system with high update rate based on 2-tap/4-phase pixel structure. Any inquiry concerning this communication should be directed to SUSAN E HODGES whose telephone number is (571)270-0498. The Examiner can normally be reached on Monday - Friday from 8:00 am (EST) to 4:00 pm (EST). If attempts to reach the Examiner by telephone are unsuccessful, the Examiner's supervisor, Brian T. Pendleton, can be reached on (571) . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /Susan E. Hodges/Primary Examiner, Art Unit 2425
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Prosecution Timeline

Dec 05, 2024
Application Filed
Sep 11, 2026
Non-Final Rejection mailed — §102 (current)

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
81%
With Interview (+13.8%)
2y 7m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 389 resolved cases by this examiner. Grant probability derived from career allowance rate.

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