DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “the reference clock unit is configured to”; “the feedback unit is configured to”; “the phase determination unit is configured to”; “the weighting unit is configured to”; “the correction unit is configured to” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 9-13, 15, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Colinet et al. – US 2012/0206177 (hereinafter Colinet) in view of Bae – US 2021/0111725.
Re claim 1, Colinet discloses:
“A phase-locked loop (Fig. 4) comprising: a reference clock unit (para. 0065, Fig. 3, 4; wherein the combination of the adjacent oscillators within the distributed network 1000, as a whole, which produce signals 108.1 – 108.4, corresponds to the claimed “reference clock unit”), a feedback unit (Fig. 4, element 106), a correction unit (Fig. 4; element 101; para. 0071), a phase discrimination unit (Fig. 4, elements 102.1 – 102.4; para. 0067, 0070) and a weighting unit (Fig. 4, element 110; para. 0071-0072); wherein
“the reference clock unit is configured to: output two or more frequency-adjustable reference clock signals to the phase discrimination unit, and the two or more reference clock signals are synchronized” (Fig. 4; para. 0067, 0070; wherein the clock signals 108.1 - 108.4 correspond the claimed “two or more frequency-adjustable reference clock signals” and that since the clock signals 108.1 – 108.4 are provided from the oscillator of adjacent nodes, they are thus “frequency-adjustable”; and wherein Colinet implies that clock signal outputs from adjacent nodes, which are derived from a master clock, are synchronized (para. 0005, 0065));
“the feedback unit is configured to: perform frequency division processing on an output voltage signal output by the phase-locked loop in a first period, to obtain a feedback signal (Fig. 4, 8 the output 106 from oscillator 101; para. 0067; 0091; wherein first period 308 teaches the claimed “first period”);
“the phase discrimination unit is configured to: determine, for each reference clock signal, a corresponding error signal for correction of the output voltage signal according to a phase difference between the reference clock signal and the feedback signal” (Fig. 4; para. 0067, 0070);
“the weighting unit is configured to: perform weighting calculation on the determined error signal, to obtain a weighted error signal (Fig. 4, element 110; para. 0071);
“the correction unit is configured to: correct an output voltage signal in a second period according to the weighted error signal, to obtain an output voltage signal output by the phase-locked loop in the second period” (Fig. 4, 8; para. 0071, 0091; wherein period 310 corresponds to the claimed “second period”);
“wherein the first period and the second period are two adjacent periods for outputting output voltage signal (Fig. 8; para. 0091; wherein periods 308 and 310 are “adjacent” to each other).”
Colinet differs from the claimed invention in that it does not explicitly discloses the above underlined claimed subject matter.
Bae, also dealing with plural reference signals PLL, discloses utilization of divider in the feedback from the oscillator to divide the frequency of the oscillating signal down to a target frequency corresponding to the reference signal (para. 0048; Fig. 1, element 1042).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the filing to have optionally incorporated the use of the divider in the feedback signal from the oscillator or Bae, into Colinet to appropriately divide the frequency of the oscillating signal down to a target frequency corresponding to the reference signal.
Re claim 2, the combination of Colinet and Bae further discloses “a filter configured to filter the weighted error signal obtained by the weighting unit” in Coliet, Fig. 4; para. 0071.
Re claim 18, see corresponding claim 2 above.
Re claim 3, the combination of Colinet and Bae further discloses “wherein the reference clock unit comprises two or more first crystal oscillators; wherein a first crystal oscillator is configured to output one of the reference clock signals” in Colinet, para. 0070; wherein the clock signals 108.1 – 108.4 are provided by oscillator of adjacent nodes, and one of the oscillator that produces signal 108.1 corresponds to the claimed “first” “oscillator”; and Bae discloses the oscillator can be “crystal oscillator” in para. 0003, 0045.
Re claim 19, see corresponding claim 3 above.
Re claim 9, the above combination further discloses “wherein the correction unit is a voltage controlled oscillator” in Colinet, Fig. 4, element 101; para 0071.
Re claim 10, the above combination further discloses “wherein the feedback unit is a frequency divider” in Bae, Fig. 1, element 1042; para. 0048.
Re claim 11, see corresponding claim 1.
Re claim 12, Colinet discloses:
“performing frequency division processing on an output voltage signal output by a phase-locked loop in a first period, to obtain a feedback signal” (Fig. 4, 8 the output 106 from oscillator 101; para. 0067; 0091; wherein first period 308 teaches the claimed “first period”;
“determining, for each reference clock signal of two or more frequency-adjustable reference clock signals, a corresponding error signal according to a phase difference between the reference clock signal and the feedback signal” (Fig. 4; para. 0067; wherein the clock signals 108.1 - 108.4 correspond the claimed “two or more frequency-adjustable reference clock signals” and that since the clock signals 108.1 – 108.4 are provided from the oscillator of adjacent nodes, they are thus “frequency-adjustable”);
“performing weighting calculation on the determined error signal, to obtain a weighted error signal” (Fig. 4, element 110; para. 0071);and
“correcting an output voltage signal of the phase-locked loop in a second period according to the obtained weighted error signal, to obtain an output voltage signal output by the phase-locked loop in the second period” (Fig. 4, 8; para. 0071, 0091; wherein period 310 corresponds to the claimed “second period”);
“wherein the first period and the second period are two adjacent periods for outputting output voltage signals (Fig. 8, para. 0091; wherein periods 308 and 310 are “adjacent” to each other); and the two or more reference clock signals are synchronized (wherein Colinet implies that clock signal outputs from adjacent nodes, which are derived from a master clock, are synchronized (para. 0065)).”
Colinet differs from the claimed invention in that it does not explicitly discloses the above underlined claimed subject matter.
Bae, also dealing with plural reference signals PLL, discloses utilization of divider in the feedback from the oscillator to divide the frequency of the oscillating signal down to a target frequency corresponding to the reference signal (para. 0048; Fig. 1, element 1042).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the filing to have optionally incorporated the use of the divider in the feedback signal from the oscillator or Bae, into Colinet to appropriately divide the frequency of the oscillating signal down to a target frequency corresponding to the reference signal.
Re claim 13, the combination of Colinet and Bae further discloses “wherein before correcting the output voltage signal of the phase-locked loop in the second period according to the obtained weighted error signal, the method further comprises: filtering the obtained weighted error signal” in Colinet, Fig. 4, element 112; para. 0071.
Re claim 15, the above combination further discloses ““wherein the reference clock unit comprises two or more first crystal oscillators; wherein a first crystal oscillator is configured to output one of the reference clock signals” in Colinet, para. 0070; wherein the clock signals 108.1 – 108.4 are provided by oscillator of adjacent nodes, and one of the oscillator that produces signal 108.1 corresponds to the claimed “first” “oscillator”; and Bae discloses the oscillator can be “crystal oscillator” in para. 0003, 0045.
Re claim 20, the above combination further discloses “wherein before determining the corresponding error signal according to the phase difference between the reference clock signal and the feedback signal, the method further comprise:
generating the two or more frequency-adjustable reference clock signals through two or more first crystal oscillators, or through on second crystal oscillator and one or more third crystal oscillators; wherein a frequency of a reference clock signal output by the second crystal oscillator is greater than a frequency of a reference clock signal output by a third crystal oscillator” in Colinet, para. 0070; wherein the clock signals 108.1 – 108.4 at the inputs of comparators 102.1 – 102.4 are provided by the oscillators of adjacent nodes, and Bae discloses the oscillator can be “crystal oscillator” in para. 0003, 0045. Note: claim 20 above is interpreted as “generating the two or more frequency-adjustable reference clock signals” (first option) either “through two or more first crystal oscillators”, or “through on second crystal oscillator and one or more third crystal oscillators; wherein a frequency of a reference clock signal output by the second crystal oscillator is greater than a frequency of a reference clock signal output by a third crystal oscillator” (second option). In this case, the combination of Colinet and Bae only need to meet the requirement of the first option of claim 20.
Allowable Subject Matter
Claims 4-8, 14, 16, 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Trumbo et al. – US 6,816,018
Sjoland – US 2024/0275392
Weeks et al. – US 11,038,511
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/DAC V HA/ Primary Examiner, Art Unit 2633