DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ritter et al. (US Publication 2004/0257748).
In re claim 1, Ritter discloses a multilayer ceramic electronic component, comprising:
a multilayer portion (208 – Figure 21A, ¶160) including a plurality of internal electrode layers (212, 214 – Figure 21A, ¶160) and a plurality of dielectric layers (¶160) stacked in a first direction;
a pair of main surface protective layers (218 – Figure 21A, ¶160) (Figure 23) located on opposite main surfaces of the multilayer portion in the first direction (Figure 21A, Figure 23);
a pair of side protective layers (upper and lower regions of the dielectric layer shown in Figure 15A, Figure 15B) located on opposite side surfaces of the multilayer portion and the pair of main surface protective layers in a second direction intersecting with the first direction (Figure 15, Figure 21A); and
a plate (224, 220 – Figure 21A, ¶161) located adjacent to each of opposite ends of each of the pair of main surface protective layers in a third direction intersecting with the second direction (Figure 21A, Figure 23)
wherein L1 ≤ L2, where L1 is a length of the plate (220, 224 – Figure 21A) in the third direction, and L2 is a length in the third direction from one end face of the multilayer portion to an end of an internal electrode layer (214 – Figure 21A) of the plurality of internal electrode layers extending from the other end face of the multilayer portion (Figure 21A).
In re claim 2, Ritter discloses the multilayer ceramic electronic component according to claim 1, as explained above. Ritter further discloses wherein the plate (224 – Figure 21A) is located on a main surface of at least one of the pair of main surface protective layers (218 – Figure 21A) in the first direction (Figure 21A).
In re claim 3, Ritter discloses the multilayer ceramic electronic component according to claim 1, as explained above. Ritter further discloses wherein the plate (224, 220 – Figure 21A) is partially located on a side surface of at least one of the pair of main surface protective layers in the second direction (Figure 21A, Figure 11; Note that the Examiner is taking the main surface protective layer to have a width that is equal to the width of the anchor tabs, or plates. Therefore, the plates are partially located on a side surface of the main surface protective layers in the second direction.).
In re claim 4, Ritter discloses the multilayer ceramic electronic component according to claim 1, as explained above. Ritter further discloses wherein T1 ≤ T2, where T1 is a thickness of the plate (224 – Figure 21A) in the first direction, and T2 is a thickness of each of the plurality of internal electrode layers (212, 214 – Figure 21A) in the first direction (¶29).
In re claim 5, Ritter discloses the multilayer ceramic electronic component according to claim 1, as explained above. Ritter further discloses wherein each of the pair of main surface protective layers (218 – Figure 21A, Figure 23) includes a main surface protective layer (any portion of the dielectric between 218 and topmost 212 – Figure 21A) end being a portion overlapping the plate when viewed in plan in the first direction, and
the plate (220, 224 – Figure 21A) has a volume percentage of 20% or more of a volume of the main surface protective layer end (Figure 21A; Note that the ‘main surface protective layer end’ is broadly being interpreted to be any portion of the dielectric layer to meet this volume limitation.).
In re claim 6, Ritter discloses the multilayer ceramic electronic component according to claim 1, as explained above. Ritter further discloses wherein the plate (220 – Figure 21A) comprises a same main component as the plurality of internal electrode layers (212, 214 – Figure 21A) (Claim 32).
In re claim 7, Ritter discloses the multilayer ceramic electronic component according to claim 6, as explained above. Ritter further discloses wherein the plate (224 – Figure 21A) comprises a ceramic component (¶163), and a content of the ceramic component in the plate is greater than or equal to a content of a ceramic component in the plurality of internal electrode layers (212, 214 – Figure 21A) (¶163).
In re claim 8, Ritter discloses the multilayer ceramic electronic component according to claim 1, as explained above. Ritter further discloses one or more plates (220, 224 – Figure 21A) stacked in the first direction (Figure 21A), the one or more plates stacked in the first direction being three or more plates (Figure 21A).
In re claim 9, Ritter discloses the multilayer ceramic electronic component according to claim 1, as explained above. Ritter further discloses wherein the length L2 is a smallest length of lengths in the third direction from one end face of the multilayer portion to ends of the plurality of internal electrode layers (212, 214 – Figure 21A, Figure 23) extending from the other end face of the multilayer portion (Figure 21A, Figure 23).
In re claim 10, Ritter discloses the multilayer ceramic electronic component according to claim 1, as explained above. Ritter further discloses wherein the length L1 is a longest portion of the plate (224, 220 – Figure 21A, Figure 23) in the third direction (Figure 21A, Figure 23).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ritter et al. (US Publication 2004/0257748) in view of Matsui et al. (US Publication 2012/0234462).
In re claim 11, Ritter discloses a method for manufacturing a multilayer ceramic electronic component, the method comprising:
fabricating a multilayer base (portion comprising dielectric, 212, 214 – Figure 21A, Figure 23, by placing a pair of main surface protectors (218 – Figure 21A, Figure 23) on opposite ends of a stack in a first direction (¶160), the stack including a plurality of electrodes (212, 214 – Figure 21A, Figure 23) and a plurality of dielectric sheets stacked in the first direction (Figure 21A);
cutting the multilayer base along a plane orthogonal to a third direction intersecting with the first direction to form a pair of cut end faces (¶162, Figure 23);
wherein the fabricating the multilayer base includes
placing sections of an electrode of the plurality of electrodes (212, 214 – Figure 21A) on a dielectric sheet in each of the pair of main surface protectors at an interval of a distance P in the third direction (Figure 21A), and
placing a base plate (220, 224 – Figure 21A) having a length in the third direction greater than or equal to the distance P at a position overlapping the interval when viewed in the first direction (Figure 21A).
Ritter does not explicitly disclose pressing the multilayer base in the first direction;
cutting the multilayer base along a plane orthogonal to a second direction intersecting with the third direction to form a pair of cut side surfaces; and
attaching side protectors to the pair of cut side surfaces.
Matsui discloses cutting the multilayer base along a plane orthogonal to a second direction intersecting with the third direction to form a pair of cut side surfaces (¶14-15); and
attaching side protectors to the pair of cut side surfaces (¶18).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the manufacturing process of Matsui to incorporate side surface protective portions while minimizing the risk of short circuiting.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Satou (US Publication 2006/0039097) Figure 3, Figure 4
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARUN RAMASWAMY/Primary Examiner, Art Unit 2847
Prosecution Insights