DETAILED ACTION
This action is responsive to 12/05/2024.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-11, 15, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawae et al. (US Pub. 2014/0049182), hereinafter Kawae182.
Regarding claim 1, Kawae182 discloses a display device (see fig. 1) that performs gradation display of a plurality of pixels in one frame including a plurality of subframes (see fig. 4 with description in [0048]-[0050]), wherein the pixels each include a light emitting element (light emitting diode EL-see fig. 3 and [0025]) and a pixel circuit that controls a current for driving the light emitting element, the pixel circuit includes a current source that generates a current for driving the light emitting element (pixel circuit 100 includes a transistor M1 (first transistor) that acts as a constant current source for controlling the amount of current flowing through the transistor M1,according to a voltage of a gate terminal of the transistor M1-see fig. 3 and [0043]), and a correction circuit that corrects a variation in the current generated by the current source (capacitive element C1 and transistor M3 of the constant current circuit 200 (see fig. 3 and [0042] and [0050]) for performing threshold voltage (Vth) compensation operation-see [0061]-[0062]), and the plurality of subframes (i.e., sub-frames SF1-SF4, see fig. 4) includes a subframe in which the light emitting element is driven after the variation is corrected by the correction circuit (sub-frame SF4 is immediately after the constant current setting period SP (herein equated to period in which variation is corrected)) and a subframe in which the light emitting element is driven without correcting the variation by the correction circuit (i.e., sub-frames SF3-SF1, see fig. 4).
Regarding claim 2, Kawae182 discloses wherein only one subframe in which the light emitting element is driven after the variation is corrected by the correction circuit is provided in the plurality of subframes (see fig. 4-the constant current setting period is performed once within a 1-frame period).
Regarding claim 3, Kawae182 discloses wherein the subframe in which the light emitting element is driven after the variation is corrected by the correction circuit is a head subframe among the plurality of subframes (SF4-see fig. 4).
Regarding claim 4, Kawae182 discloses wherein two or more subframes in which the light emitting element is driven after the variation is corrected by the correction circuit are provided in the plurality of subframes (see fig. 4, sub-frames SF4-SF1).
Regarding claim 8, Kawae182 discloses wherein each of the plurality of pixels is connected to any one of a plurality of gate lines (scanning signal line SCAN-see fig. 3 and [0031]), and a plurality of the correction circuits included in the plurality of pixels corrects variations in current generated by the plurality of current sources in the plurality of pixels connected to the plurality of gate lines (capacitive element C1 and transistor M3 of the constant current circuit 200 (see fig. 3 and [0042] and [0050]) for performing threshold voltage (Vth) compensation operation-see [0061]-[0062]) at a same timing (the constant current period is decided such that all pixels of the pixel circuit 100 have the same period-see [0050]).
Regarding claim 9, Kawae182 discloses wherein the pixel circuit includes a storage unit that stores pixel data (transistor M4 and capacitor Cs are herein equated to a storage unit-see fig. 3 and [0047]), and a first switching element that switches, for each of the plurality of subframes, whether or not to supply the light emitting element with a current corrected by the correction circuit on a basis of the pixel data stored in the storage unit (see fig. 3 with description in [0046]-transistor M2 (herein equated to claimed first switching element) selectively supplies current to the light emitting diode according to a voltage of its gate terminal).
Regarding claim 10, Kawae182 discloses wherein the current source includes a second switching element cascode-connected to the first switching element (M1 and M2 are cascode-connected-see fig. 3), and the correction circuit corrects a threshold voltage of the second switching element (see [0061]-[0062]).
Regarding claim 11, Kawae182 wherein the first switching element is turned on or off according to the pixel data stored in the storage unit (see fig. 3-gate of M2 is controlled by output of the storage unit), and when the first switching element and the second switching element are turned on, the pixel circuit causes a current corrected according to a threshold voltage of the second switching element to flow from the second switching element to the light emitting element through the first switching element (see fig. 3 and [0061]-[0063]).
Regarding claim 15, Kawae182 discloses wherein conductivity types of the first switching element and the second switching element are same (see fig. 3-M1 and M2 are both P-channel transistors).
Regarding claim 19, Kawae182 discloses wherein light emission periods of the light emitting elements in the plurality of subframes are different from each other (see fig. 4 with description in [0048]-sub-frame periods SF1 to SF4 have different lengths, and light emission and non-light emission of a light emitting diode EL are controlled by the sub-frame period).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawae182.
Regarding claim 16, Kawae182 does not appear to expressly disclose wherein conductivity types of the first switching element and the second switching element are different from each other.
However, using switching elements having a same conductivity would have been an obvious design choice to a person of ordinary skill in the art before the effective filing date of the claimed invention in view of the combined teachings of Kawae182, and simply would have constituted choosing from a finite number of identified, predictable solutions for selecting the first and the second switching elements, with a reasonable expectation of success.
Regarding claim 20, Kawae182 does not appear to expressly disclose wherein light emission periods of the light emitting elements in the plurality of sub-frames are same.
However, Kawae182, in for example, [0048] teaches that each sub-frame period has a binary code weighted rate, which is conceivable that the binary code weighted rate can be designed to be the same for all the sub-frames as an obvious design choice, and which would have constituted choosing from a finite number of identified, predictable solutions for selecting the first and the second switching elements, with a reasonable expectation of success.
Claims 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawae182 in view of Kawae et al. (US Pub. 2014/0152709), hereinafter Kawae709.
Regarding claim 5, Kawae182 does not appear to expressly disclose wherein the subframe in which the light emitting element is driven after the variation is corrected by the correction circuit includes two or more subframes not adjacent to each other among the plurality of subframes.
Kawae709, in for example, fig. 4 with description in [0054], teaches that while the constant set period SP appears once in the one frame period as shown in fig. 4, the number of the constant current set period SP is not limited there to or thereby. For instance, the constant current set period may appear three times during two frame periods or the constant current set period SP may not appear during each one frame period, e.g., the constant current set period may appear twice during three frame periods.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Kawae709 with the invention of Kawae182 such that the number of sub-frames in which the correction can be performed within a frame period or frame periods can be varied as desired, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., providing a display device and a driving method thereof that reduces the number of transistors per one pixel to realize a high definition image, reduces influence on display images due to variation in characteristic deviation of the transistors, and improves contrast-see [0086]).
Regarding claim 6, Kawae182 does not appear to expressly disclose wherein the subframe in which the light emitting element is driven after the variation is corrected by the correction circuit includes two or more adjacent subframes among the plurality of subframes.
Kawae709, in for example, fig. 4 with description in [0054], teaches that while the constant set period SP appears once in the one frame period as shown in fig. 4, the number of the constant current set period SP is not limited there to or thereby. For instance, the constant current set period may appear three times during two frame periods or the constant current set period SP may not appear during each one frame period, e.g., the constant current set period may appear twice during three frame periods.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Kawae709 with the invention of Kawae182 such that the number of sub-frames in which the correction can be performed within a frame period or frame periods can be varied as desired, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., providing a display device and a driving method thereof that reduces the number of transistors per one pixel to realize a high definition image, reduces influence on display images due to variation in characteristic deviation of the transistors, and improves contrast-see [0086]).
Regarding claim 7, Kawae182 does not appear to expressly disclose wherein the subframe in which the light emitting element is driven after the variation is corrected by the correction circuit includes a predetermined number of adjacent subframes including a head subframe among the plurality of subframes.
Kawae709, in for example, fig. 4 with description in [0054], teaches that while the constant set period SP appears once in the one frame period as shown in fig. 4, the number of the constant current set period SP is not limited there to or thereby. For instance, the constant current set period may appear three times during two frame periods or the constant current set period SP may not appear during each one frame period, e.g., the constant current set period may appear twice during three frame periods.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Kawae709 with the invention of Kawae182 such that the number of sub-frames in which the correction can be performed within a frame period or frame periods can be varied as desired, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., providing a display device and a driving method thereof that reduces the number of transistors per one pixel to realize a high definition image, reduces influence on display images due to variation in characteristic deviation of the transistors, and improves contrast-see [0086]).
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawae182 in view of Sheth et al. (US Pub. 2022/0165208), hereinafter Sheth.
Regarding claim 12, Kawae182 does not appear to expressly disclose further comprising: a bias signal line that supplies a bias signal common to a plurality of the correction circuits included in the plurality of pixels, wherein the second switching element is turned on when the bias signal reaches a predetermined voltage level.
Sheth is relied upon to teach a bias signal line that supplies a bias signal common to a plurality of the correction circuits included in the plurality of pixels (see Sheth et al. 2022/0165208-see figs. 2A-2B with description in [0046] and [0058], which illustrated a conductor (219, 333) serving as a bias signal voltage line, as coupled to voltage Vss (herein, bias signal)), wherein the second switching element is turned on when the bias signal reaches a predetermined voltage level (current source FET (215, 326) is controlled by Vss (bias signal)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Sheth with the invention of Kawae182 by including a bias signal line for applying a bias signal to turn to control a gate of the second switching element, as taught by Sheth, in order to provide a stable reference current to the get of the current source FET 215 (second transistor)-(see fig. 2A and [0046]-[0047]).
Claims 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawae182 in view of Sheth, and further in view of Knez et al. (US Patent 11,049,448), hereinafter Knez.
Regarding claim 13, Kawae182 discloses wherein the correction circuit includes a third switching element connected between a gate and a drain of the second switching element (M3-see fig. 3).
However, Kawae182 in view of Sheth does not appear to expressly teach a first capacitor connected between the gate of the second switching element and the bias signal line, and a second capacitor connected between the gate and the source of the second switching element.
Knez is relied upon to teach a first capacitor connected between the gate of the second switching element and the bias signal line (see, for example, fig. 31, which illustrates a first capacitor C1 coupled between a voltage line VDDEL (herein bias signal line) and a gate of a transistor (second switching element)), and a second capacitor connected between the gate and the source of the second switching element (second capacitor C2 is connected between one terminal of the transistor and the gate of the transistor).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Knez with the inventions of Kawae182 and Sheth to include one or more capacitors coupled between the bias signal line and a gate of the second transistor, and between a gate and a source of the second transistor, as taught by Knez, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., having one more parasitic capacitors for storage within the pixel circuit).
Regarding claim 14, Kawae182 discloses wherein the plurality of the correction circuits included in the plurality of pixels synchronously turns on or off a plurality of the first switching elements, synchronously turns on or off a plurality of the second switching elements, and synchronously turns on or off a plurality of the third switching elements (see [0050]-the constant current setting period is set during a same period for all pixels).
Claims 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawae182 in view of Lu et al. (US Pub. 2020/0135105), hereinafter Lu.
Regarding claim 17, Kawae182 discloses wherein the first switching element is connected to the anode of the light emitting element (M2 is connected to anode of the light emitting element (EL)-see fig. 3), and a cathode of the light emitting element is set to a second reference voltage (i.e., cathode of EL is connected to power line GL2 (ELVSS)-see fig. 3 and [0036]).
Kawae182 does not appear to expressly disclose further comprising: a fourth switching element that switches whether or not to set an anode of the light emitting element to a first reference voltage.
Lu is relied upon to teach a fourth switching element that switches whether or not to set an anode of the light emitting element to a first reference voltage (see, for example, fig. 1 with description in [0033], which teaches a transistor T3 (equated to claimed fourth transistor) that may be switched on by a scan signal SCAN(n-1) to apply an initialization voltage (INIT) to an anode of a light emitting element (OLED)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Lu with the invention of Kawae182 by including transistor for applying an initialization voltage to an anode of the light emitting element, as taught by Lu, in order to clear memory effects from a previous frame (see [0033]).
Regarding claim 18, Lu is further relied upon to teach a fourth switching element that switches whether or not to set a cathode of the light emitting element to a first reference voltage (see fig. 7 with description in [0077]-transistor T3 applies initialization voltage (INIT) to cathode of the OLED), wherein the first switching element is connected to the cathode of the light emitting element (T4 (equated to first switching element) is connected to the cathode of the OLED-see fig. 7), and an anode of the light emitting element is set to a second reference voltage (anode of the OLED is coupled to ELVDD (second reference voltage)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Lu with the invention of Kawae182 by including transistor for applying an initialization voltage to an anode of the light emitting element, as taught by Lu, in order to clear memory effects from a previous frame (see [0033]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571)272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SARDIS F AZONGHA/Primary Examiner, Art Unit 2627
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