Prosecution Insights
Last updated: April 19, 2026
Application No. 18/872,378

SUBSTRATE FOR PRINTED CIRCUIT BOARD AND PRINTED CIRCUIT BOARD

Final Rejection §103
Filed
Dec 06, 2024
Examiner
RUMMEL, IAN A
Art Unit
1785
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Sumitomo Electric Printed Circuits Inc.
OA Round
2 (Final)
56%
Grant Probability
Moderate
3-4
OA Rounds
3y 4m
To Grant
76%
With Interview

Examiner Intelligence

Grants 56% of resolved cases
56%
Career Allow Rate
318 granted / 568 resolved
-9.0% vs TC avg
Strong +20% interview lift
Without
With
+19.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
27 currently pending
Career history
595
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
55.0%
+15.0% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 568 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 5-6, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kiya et al., US 2017/0327630 A1, in view of Markovich, US 5055342. Regarding claims 1 and 10, Kiya teaches a substrate for a printed circuit board comprising a base film made of a fluororesin (Abstract) and a wiring pattern formed from an electrically conductive layer comprising a plurality of particles ([0072], [0099]), wherein the content of nitrogen on the surface of the film has a nitrogen content of 0.2 atomic percent of more (Abstract, [0054]-[0055]). Note that although Kiya does not explicitly refer to the conductive particles as being “bonded together,” Kiya teaches that a conductive layer for the circuit board may be formed by performing electroplating on the conductive particles, which would necessarily bind the particles together. The teachings of Kiya differ from the present invention in that Kya does not teach the presence of silica particles in the fluororesin film. Markovish, however, teaches the addition of silica particles to fluororesins used in the creation of circuit boards in order to improve the dielectric properties and thermal expansion properties of the material (Abstract, col. 2 ln. 45-64). It would have been obvious to one of ordinary skill in the art to add silica particles to the fluororesin of Kiya, because doing so would improve the dielectric and thermal expansion properties of the material. Regarding claim 3, Kiya teaches a substrate for a circuit board as described above, and teaches that the thickness of the conductive layer may be 2 – 50 microns ([0074]). Regarding claims 5 and 6, Kiya teaches electroplating or electroless plating of copper onto the electrically conducting layer ([0073], [0099]). Regarding claim 9, Kiya teaches that the fluororesin may be polytetrafluoroethylene ([0041], [[0065]). Regarding claim 11, Markovich teaches that the silica particles may have a size of 7 microns or less (Abstract), or 1.1 microns specifically (col. 4 ln. 2-4). Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kiya and Markovich, as applied above, and further in view of Schroder et al., US 2008/0020304 A1. Regarding claims 2 and 4, Kiya teaches a substrate for a circuit board as described above. The teachings of Kiya differ from the present invention in that although Kiya teaches the use of metal nanoparticles, Kiya does not teach any specific metal or size for the particles. Schroder, however, teaches that when using metal particles as a substrate for metal deposition in the formation of circuit boards, the particles may be copper or silver particles ([0028], [0046]) having a size of 500 nm or less ([0017]). It would have been obvious to one of ordinary skill in the art to use copper or silver particles having a size of 500 nm or less as the metal particles of Kiya, as Schroder explicitly teaches copper or silver particles with a size of 500 nm or less to be appropriate when forming patterns on wiring boards via deposition. Claims 1, 3, 5-6, 9-10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kiya et al., US 2017/0327630 A1, in view of Arthur et al., US 4849284. Regarding claims 1 and 10, Kiya teaches a substrate for a printed circuit board comprising a base film made of a fluororesin (Abstract) and a wiring pattern formed from an electrically conductive layer comprising a plurality of particles ([0072], [0099]), wherein the content of nitrogen on the surface of the film has a nitrogen content of 0.2 atomic percent of more (Abstract, [0054]-[0055]). Note that although Kiya does not explicitly refer to the conductive particles as being “bonded together,” Kiya teaches that a conductive layer for the circuit board may be formed by performing electroplating on the conductive particles, which would necessarily bind the particles together. The teachings of Kiya differ from the present invention in that Kya does not teach the presence of silica particles in the fluororesin film. Arthur, however, teaches the addition of silica particles to fluororesins used in the creation of circuit boards in order to improve the dielectric properties and thermal expansion properties of the material (Abstract, col. 2 ln. 33-54). It would have been obvious to one of ordinary skill in the art to add silica particles to the fluororesin of Kiya, because doing so would improve the dielectric and thermal expansion properties of the material. Regarding claim 3, Kiya teaches a substrate for a circuit board as described above, and teaches that the thickness of the conductive layer may be 2 – 50 microns ([0074]). Regarding claims 5 and 6, Kiya teaches electroplating or electroless plating of copper onto the electrically conducting layer ([0073], [0099]). Regarding claim 9, Kiya teaches that the fluororesin may be polytetrafluoroethylene ([0041], [[0065]). Regarding claim 12, although Arthur does not teach any specific volume ratio for the silica particles relative to the fluororesin, Arthur teaches that the particles may be present in an amount of 62-64 wt% while the fluoropolymer may be present in an amount of 34-36 wt% (col. 4 ln. 46-66), which would result in a volume ratio of greater than 1.2 based on the relative densities of the fluorpolymer and silica (both approximately 2.2). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ian A Rummel whose telephone number is (571)270-5692. The examiner can normally be reached Monday - Thursday and alternating Fridays, 8:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Ruthkosky can be reached at (571) 272-1291. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IAN A RUMMEL/Primary Examiner, Art Unit 1785
Read full office action

Prosecution Timeline

Dec 06, 2024
Application Filed
Aug 25, 2025
Non-Final Rejection — §103
Oct 28, 2025
Response Filed
Feb 06, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12601970
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2y 5m to grant Granted Apr 14, 2026
Patent 12589607
PRINTING PROCESSES FOR PRODUCING TEXTURED IMAGES
2y 5m to grant Granted Mar 31, 2026
Patent 12569878
PLATED STEEL SHEET
2y 5m to grant Granted Mar 10, 2026
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COATING COMPOSITION AND LAMINATE
2y 5m to grant Granted Feb 17, 2026
Patent 12545797
INKJET INKS FOR METALLIC PRINTED IMAGES
2y 5m to grant Granted Feb 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
56%
Grant Probability
76%
With Interview (+19.7%)
3y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 568 resolved cases by this examiner. Grant probability derived from career allow rate.

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