DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “program module” in claim 27 and measuring device in claims 28 and 39.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 26-30 and 37-41 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 26 and 37, each of these claims recites "said non-circular pattern for the semi-conductor chips" in their first and second lines. There is insufficient antecedent basis for a “non-circular pattern” or “semi-conductor chips” in these claims. It is unclear if a pattern of chips is necessary to meet the claims and what would constitute a pattern of chips in the context of the claim. Are these claims intended to be dependent from claims 25 and 36 respectively? For the purposes of this examination, these claims will be interpreted as best can be understood by examiner and is explained in the rejection below.
Claim limitation “program module” in claim 27 invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Claim 27 recites the “program module” being configured to perform several different functions including “forming a 3D volumetric digital model of the crystal from an output of the scanner,” “recording 3D spatial coordinates of defects detected by the scanner,” and “compute an offset position of a slicing tool along a selected crystal axis configured to have a minimum number of wafers with defects.” As the term “program module” is a generic term which does not include or imply any particular structure and is defined solely by its function, this claim limitation invokes interpretation under 112f. However, the specification does not recite any structure for performing the entire claimed function. A “program module” is discussed on page 3, paragraph 6. However, this citation merely repeats the functions discussed in the claims and does not define any structure for performing the functions. The figures do not appear to show any structure capable of performing these functions. As claim 27 is directed towards a system for producing wafers, a person of ordinary skill would not know what structure is necessary to perform the function and meet the claim (see also 112a rejection below). Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 28-30 and 38-41 are rejected as indefinite due to their dependency upon rejected claim 27.
Further regarding claim 38, this claim defines “an absolute value of the offset is calculated from a reference position on a surface of the crystal prior to crystal coring operation.” There is insufficient antecedent basis for a crystal coring operation and it is unclear if this operation is necessary to meet the claim. Furthermore, this claim defines method steps of calculating an absolute value and coring, while claim 38 (and 27 from which it depends) is directed to a system for inspecting a crystal. It is unclear what structure or function is being imparted to the system, as the steps of calculating the absolute value and coring are not connected to any particular structure. If the calculation step can be performed by a human in their mind, how does this further define the structure of claim 27? Is the coring operation an intended later step to occur after using the system, or must there be structure configured to perform coring of the crystal in the system itself? For the purposes of this examination, rather than being read as defining any particular structure, this claim will be read as defining a system which would allow a user to perform the claimed calculating and coring steps by any method separate from the claimed system, as this is examiner’s best understanding of the broadest reasonable interpretation of the claim and the claimed steps are not connected to the claimed system and appear to be an intended use.
Claims 39-41 are rejected as indefinite due to their dependency upon rejected claim 38.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 27-30 and 38-41 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above, the disclosure does not provide adequate structure to performed the claimed functions of “forming a 3D volumetric digital model of the crystal from an output of the scanner,” “recording 3D spatial coordinates of defects detected by the scanner,” or “compute an offset position of a slicing tool along a selected crystal axis configured to have a minimum number of wafers with defects” as recited in claim 27 (and therefore present in claims 28-30 and 38-41 dependent therefrom). Therefore, the specification does not demonstrate that applicant has made a system which achieves these claimed functions, because the invention is not described with sufficient detail that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-20, 23-30, and 38-41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meyer (WO 2012/150517, previously cited) in view of Mitamura (WO 2014/162657, previously cited).
Regarding claim 16, Meyer teaches a method of producing wafers or discs from an industrially grown crystal comprising the steps of: scanning a crystal in volume and forming a 3D volumetric digital model of the crystal (p 12, line 29), measuring one or more crystal axes provided by a crystalline structure of the crystal, and recording this crystal axis in said 3D model of the crystal (p 12, lines 29-31), coring out one or more cores from the crystal in a selected crystal direction which is parallel to one of said crystal axes or at a defined angle with respect to said crystal axis (p 12, lines 30-34; figs 1-2), slicing at least one of said one or more cores orthogonally (p 17, lines 16-20; cutting plane is aligned with theoretical plane which is orthogonal to crystal direction defined by crystal axis) to the selected crystal direction with a wafer slicing machine comprising a slicing tool (“wire cutting device”; fig 5) comprising a plurality of cutting wires (11; p 13, lines 21-25) or blades spaced at a regular slicing pitch configured to cut wafers of identical thicknesses from the core (as shown in figs 13-14).
Meyer does not teach recording 3D spatial coordinates of defects during said scanning, or computing an offset position of the slicing tool along the selected crystal direction configured to have a minimum number of defects, or adjusting the position of the slicing tool relative to the core along the selected crystal direction according to the computed offset. Mitamura teaches a method of producing wafers from a grown crystal comprising the steps of recording spatial coordinates of defects detected during scanning (paragraph starting line 358; ingot is measured to determine location where defect is likely to occur; measurements are mapped to coordinates as shown in fig 4); and computing an offset position of the slicing tool along the selected crystal direction (paragraph starting line 381; cutting position is adjusted based on defect location) configured to have a minimum number of wafers with defects (paragraph starting line 470), and adjusting the position of the slicing tool relative to the core along the selected crystal direction according to the computed offset (paragraph starting line 434). It would have been obvious for a person having ordinary skill in the art before the effective filing date of the claimed invention to record spatial coordinates of defects detected during scanning onto the 3D model created by Meyer (and thus including 3D spatial coordinates), compute an offset position of the slicing tool along the selected crystal direction configured to have a minimum number of wafers with defects, and adjust the position of the slicing tool relative to the core along the selected crystal direction according to the computed offset, as this allows the method to automatically produce wafers without defects as taught by Mitamura (paragraphs starting lines 434 and 470).
Regarding claim 17, Meyer, as modified by Mitamura, teaches all the limitations of claim 16 as described above. Mitamura, which teaches the claimed offset position as detailed above, further teaches the offset position has an amplitude (paragraph starting line 399; the amount the cutting position changes from the initial position has an amplitude). While not explicitly teaching the amplitude is in a range of 0 to said slicing pitch thickness of the wafers, Mitamura does teach the amplitude depends on the measured position of the defects (lines 381-386), and therefore would calculate an offset within the claimed range in the case where the defect can be avoided with an offset of less than the slicing pitch thickness. Additionally, Mitamura teaches using a small offset results in improved yield (paragraph starting line 427). Therefore, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the claimed invention to use an offset position with an amplitude varying in a range of 0 to the slicing pitch of the thickness of the wafers of Meyer, as this results in an improved yield while avoiding defects as taught by Mitamura (paragraph starting line 427).
Regarding claim 18, Meyer, as modified, teaches all the limitations of claim 16 as described above. Meyer further does not teach the scanning includes optical scanning (Meyer uses X-ray scanning). Mitamura further teaches the method for producing wafers including a step of optically scanning the crystal (paragraph starting line 358; using infrared light). It would have been obvious for a person having ordinary skill in the art before the effective filing date of the claimed invention to substitute the optical scanning of Mitamura for the X-ray scanning of Meyer, as these are known alternatives for scanning a wafer crystal and optical scanning achieves the predicable result of determining a composition of the crystal as taught by Mitamura (paragraph starting line 358).
Regarding claims 19-20, Meyer, as modified, teaches all the limitations of claim 16 as described above. Meyer further teaches the at least one core is placed in a holder (2; fig 7), the holder and said at least one core positioned in the slicing machine (as shown in fig 5); and wherein the crystal axis of the core is measured once more after the at least one core has been cut out of the crystal (measurement of core crystal axis described p 15, lines 12-16, is additional to the crystal scanning described p 12, lines 29-32) and the core axis position is adjusted by means of the holder such that the slicing tool cuts wafers orthogonally to the adjusted crystal axis (p14, lines 22-28; as shown in fig 7, arrows indicate crystal axes adjusted to be orthogonal to vertical cutting direction).
Regarding claim 23, Meyer, as modified, teaches all the limitations of claim 16 as described above. Meyer does not teach the scanning step of defects and geometry of the crystal is performed after a cropping operation of top and/or bottom ends of the raw crystal. Mitamura further teaches the method of producing wafers includes cropping a top and/or bottom ends of a raw crystal prior to subsequent processing operations (paragraph starting line 15; “top and bottom portions” of the grown crystal are cut off). It would have been obvious for a person having ordinary skill in the art before the effective filing date of the claimed invention to perform a cropping operation of top and/or bottom ends of the crystal before the scanning step of defects and geometry of the crystal of Meyer, as this cropping step is a known standard step of the Czochraslki crystal growing method (Mitamura lines 15-18), which is employed by Meyer (Meyer p 12, lines 23-25), and which achieves the predictable result of removing portions of the crystal which cannot be used as products as taught by Mitamura (paragraph starting line 15).
Regarding claim 24, Meyer, as modified, teaches all the limitations of claim 16 as described above. Meyer further teaches the crystal comprises a plurality of equivalent crystal axes or a plurality of equivalent crystal directions (fig 1; p 12, lines 30-34; each core is along an equivalent crystal axis or direction), the method comprising generating flat planes intersecting said ate last one of said one or more cores or the wafers (several flat planes are generated through the slicing step shown in fig 5), the flat planes parallel to an axis of the at least one core and orthogonal to the crystal axes (as shown in fig 5, flat planes cut from a core along the M-axis (as described p 13, lines 9-14), are orthogonal to the M-axis and parallel to the A-axis). Mitamura further teaches the computing step, which is included in the method as described in the rejection of claim 16 above, comprises computing a number of defects between said flat planes and an outer contour of the core or wafers (paragraph starting line 387; determines locations of likely defects), selecting one of said flat planes for cutting for which a maximum number of defects are positioned within a waste area between the flat plane and the outer contour (paragraph starting line 470; selects cutting planes for wafers to ensure defects are removed as a waste product instead of being included in one of the cut wafers).
Regarding claim 25, Meyer, as modified by Mitamura, teaches all the limitations of claim 16 as described above. Mitamura further teaches (as a part of the computing step included as described in the rejection of claim 16 above) a non-circular pattern (as broadly claimed, the slicing pattern for forming the wafers can be considered a pattern) being a pattern for semi-conductor chips to be cut out of a wafer (note that chips are not necessary to meet the claim) are oriented according to one of a plurality of crystal directions (fig 5; cuts oriented perpendicular to crystal direction along central axis of the ingot) computed such that a minimum number of defects are found within an area of the chips or within a minimum number the chips, and a maximum number of defects are found within a waste area between an outer contour of the pattern of chips and an outer circular periphery of the wafer (the pattern is calculated in order to ensure the cut usable wafers have no defects while relegating defects to an outer circular periphery outside the usable wafers; paragraphs starting line 434 and 470).
Regarding claim 26, Meyer, as modified by Mitamura, teaches all the limitations of claim 16 as described above. Meyer further teaches a pattern of chips is included in the 3D volumetric digital model of the crystal (as the cut wafers provide a substrate for the formation of semiconductor chips as described p 2 lines 23-28, the cutting pattern which forms the wafer surfaces can be considered the pattern of chips as broadly claimed) for computation of the offset (as described in the rejection of claim 16 above, the model is used to compute the offset). Mitamura further teaches the computation (included in the method as described in the rejection of claim 16 above) takes into account defects positioned in a waste area between an outer diameter of the wafer and the chips to be cut out (note that the chip cutting step is not actively claimed as a part of the method) of the wafer (as best understood, Mitamura lines 463-474 describe cutting the wafers such that defects are in a waste area between an outer area of the ingot and a usable wafer from which chips can subsequently be cut).
Regarding claim 27, Meyer teaches a system for inspecting an industrially grown crystal to produce wafers from the industrially grown crystal comprising: a scanner for scanning a crystal in volume (p 12, lines 29-32; described by the measurement of the crystal outer surface) and a program module configured for forming a 3D volumetric digital model of the crystal from an output of the scanner (p 12, lines 29-31 describes forming a 3D model from the scan).
Meyer does not teach the program module recording 3D spatial coordinates of defects detected by the scanner, or computing an offset position of a slicing tool along a selected crystal axis configured to have a minimum number of wafers with defects. Mitamura teaches a system for producing wafers from a grown crystal including a program module (paragraph starting line 192; “computer”) configured to record spatial coordinates of defects detected during scanning (paragraph starting line 358; ingot is measured to determine location where defect is likely to occur; measurements are mapped to coordinates as shown in fig 4, which would be 3D when applied to the system of Meyer); and compute an offset position of a slicing tool along a selected crystal axis (paragraph starting line 381; cutting position is adjusted based on defect location) configured to have a minimum number of wafers with defects (paragraph starting line 470). It would have been obvious for a person having ordinary skill in the art before the effective filing date of the claimed invention to configure a program module to perform the functions of recording spatial coordinates of defects detected during scanning onto the 3D model created by Meyer (thus including 3D spatial coordinates), and computing an offset position of a slicing tool along the selected crystal axis configured to have a minimum number of wafers with defects, as this allows the system to automatically produce wafers without defects as taught by Mitamura (paragraphs starting lines 434 and 470).
Regarding claims 28-29, Meyer, as modified, teaches all the limitations of claim 27 as described above. Meyer further teaches the system comprising a measuring device (interpreted under 112f to include an optical or x-ray measurement system and functional equivalents thereof) for measuring one or more crystal axes provided by a crystalline structure of the crystal, and recording said one or more crystal axes in said 3D model of the crystal (p 1, lines 16-19); and further comprising a coring device (“hollow drill”) for cutting out one or more cylindrical cores from the crystal in a selected crystal axis direction (p 12, lines 30-34), and a wafer slicing machine comprising a slicing tool (6) comprising a plurality of cutting wires (11; as shown in fig 5) or blades spaced at a regular slicing pitch configured to cut wafers of identical thicknesses (identical thickness shown in fig 13) from at least one of said one or more cylindrical cores (p 13, lines 21-25).
Regarding claim 30, Meyer, as modified, teaches all the limitations of claim 27 as described above. Meyer further discloses the system is configured to carry out a method of slicing wafers or discs from the industrially grown crystal comprising the steps of: scanning a crystal in volume and forming a 3D volumetric digital model of the crystal (p 12, line 29), measuring one or more crystal axes provided by a crystalline structure of the crystal, and recording this crystal axis in said 3D model of the crystal (p 12, lines 29-31), coring out one or more cores from the crystal in a selected crystal direction which is parallel to one of said crystal axes or at a defined angle with respect to said crystal axis (p 12, lines 30-34; figs 1-2), slicing the at least one of said one or more cores orthogonally (p 17, lines 16-20; cutting plane is aligned with theoretical plane which is orthogonal to crystal direction defined by crystal axis) to the selected crystal direction with a wafer slicing machine comprising the slicing tool (“wire cutting device”; fig 5) comprising a plurality of cutting wires (11; p 13, lines 21-25) or blades spaced at a regular slicing pitch configured to cut wafers of identical thicknesses from said at least one of said one or more cores (as shown in figs 13-14 ).
Meyer does not teach the system configured for recording 3D spatial coordinates of defects during said scanning, or computing an offset position of the slicing tool along the selected crystal direction configured to have a minimum number of defects, or adjusting the position of the slicing tool relative to the core along the selected crystal direction according to the computed offset. Mitamura further teaches the system configured to perform the steps of recording spatial coordinates of defects detected during scanning (paragraph starting line 358; ingot is measured to determine location where defect is likely to occur; measurements are mapped to coordinates as shown in fig 4); and computing an offset position of the slicing tool along the selected crystal direction (paragraph starting line 381; cutting position is adjusted based on defect location) configured to have a minimum number of wafers with defects (paragraph starting line 470), and adjusting the position of the slicing tool relative to the core along the selected crystal direction according to the computed offset (paragraph starting line 434). It would have been obvious for a person having ordinary skill in the art before the effective filing date of the claimed invention to configure the system of Meyer to record spatial coordinates of defects detected during scanning onto the 3D model created by Meyer (thus including 3D spatial coordinates), compute an offset position of the slicing tool along the selected crystal direction configured to have a minimum number of wafers with defects, and adjust the position of the slicing tool relative to the core along the selected crystal direction according to the computed offset, as this allows the system to automatically produce wafers without defects as taught by Mitamura (paragraphs starting lines 434 and 470).
Regarding claim 38, Meyer, as modified, teaches all the limitations of claim 27 as described above. Meyer further teaches (as best can be understood; see 112b rejection above) an absolute value of the offset can be calculated from a reference position on a surface of the crystal prior to a crystal coring operation (as best understood, the combined system of Meyer and Mitamura discussed in the rejection of claim 27 above would allow such a calculation and subsequent coring, as it provides the offset as described in the rejection of claim 27 above; as best understood no particular structure is being defined here and the claimed steps are not connected to the claimed system).
Regarding claims 39-40, Meyer, as modified, teaches all the limitations of claim 38 as described above. Meyer further teaches the system comprising a measuring device (interpreted under 112f to include an optical or x-ray measurement system and functional equivalents thereof) for measuring one or more crystal axes provided by a crystalline structure of the crystal, and recording said one or more crystal axes in said 3D model of the crystal (p 1, lines 16-19); and further comprising a coring device (“hollow drill”) for cutting out one or more cylindrical cores from the crystal in a selected crystal axis direction (p 12, lines 30-34), and a wafer slicing machine comprising a slicing tool (6) comprising a plurality of cutting wires (11; as shown in fig 5) or blades spaced at a regular slicing pitch configured to cut wafers of identical thicknesses (identical thickness shown in fig 13) from at least one of said one or more cylindrical cores (p 13, lines 21-25).
Regarding claim 41, Meyer, as modified, teaches all the limitations of claim 38 as described above. Meyer further discloses the system is configured to carry out a method of slicing wafers or discs from the industrially grown crystal comprising the steps of: scanning a crystal in volume and forming a 3D volumetric digital model of the crystal (p 12, line 29), measuring one or more crystal axes provided by a crystalline structure of the crystal, and recording this crystal axis in said 3D model of the crystal (p 12, lines 29-31), coring out one or more cores from the crystal in a selected crystal direction which is parallel to one of said crystal axes or at a defined angle with respect to said crystal axis (p 12, lines 30-34; figs 1-2), slicing the at least one of said one or more cores orthogonally (p 17, lines 16-20; cutting plane is aligned with theoretical plane which is orthogonal to crystal direction defined by crystal axis) to the selected crystal direction with a wafer slicing machine comprising the slicing tool (“wire cutting device”; fig 5) comprising a plurality of cutting wires (11; p 13, lines 21-25) or blades spaced at a regular slicing pitch configured to cut wafers of identical thicknesses from said at least one of said one or more cores (as shown in figs 13-14 ).
Meyer does not teach the system configured for recording 3D spatial coordinates of defects during said scanning, or computing an offset position of the slicing tool along the selected crystal direction configured to have a minimum number of defects, or adjusting the position of the slicing tool relative to the core along the selected crystal direction according to the computed offset. Mitamura further teaches the system configured to perform the steps of recording spatial coordinates of defects detected during scanning (paragraph starting line 358; ingot is measured to determine location where defect is likely to occur; measurements are mapped to coordinates as shown in fig 4); and computing an offset position of the slicing tool along the selected crystal direction (paragraph starting line 381; cutting position is adjusted based on defect location) configured to have a minimum number of wafers with defects (paragraph starting line 470), and adjusting the position of the slicing tool relative to the core along the selected crystal direction according to the computed offset (paragraph starting line 434). It would have been obvious for a person having ordinary skill in the art before the effective filing date of the claimed invention to configure the system of Meyer to record spatial coordinates of defects detected during scanning onto the 3D model created by Meyer (thus including 3D spatial coordinates), compute an offset position of the slicing tool along the selected crystal direction configured to have a minimum number of wafers with defects, and adjust the position of the slicing tool relative to the core along the selected crystal direction according to the computed offset, as this allows the system to automatically produce wafers without defects as taught by Mitamura (paragraphs starting lines 434 and 470).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meyer and Mitamura as applied to claim 16 above, and further in view of Wang (WO 2021/208365, previously cited).
Regarding claim 21, Meyer, as modified, teaches all the limitations of claim 16 as described above. Meyer does not teach when coring out said one or more cores, at least one of said one or more cores is positioned such that a minimum number of defects in a largest diameter core are found by computation using the 3D model in the wafers to be cut out of the crystal. Wang teaches a method of producing wafers or discs from a crystal including a step of when coring out said one or more cores (cutting cores 3-5, 3-6 from crystal 3 as described [0073]), at least one of said one or more cores is positioned and cut out of the crystal based on computation using a model, such that the at least one of said one or more cores is largest (all cores avoid defects regardless of size) and is positioned in a region of the crystal in which a minimum number of defects are found in the wafers to be cut out of the crystal ([0073]; using instruments to locate and avoid the defects). It would have been obvious for a person having ordinary skill in the art before the effective filing date of the claimed invention to use the 3D volumetric model of Meyer to compute a position for cutting the cores from the crystal (since this positioning applies to all cores, this would necessarily avoid defects for any core considered to be “a largest diameter core” as claimed), such that a minimum number of defects are found in the wafers to be cut out of the crystal, as this avoiding of defects increases the quality and yield of the resulting devices as taught by Wang ([0073], [0004]).
Allowable Subject Matter
Claims 22 and 31-36 are allowed. Claim 37 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: Claims 22 and 31-37 are allowable for the reasons indicated in the previous office action.
Response to Arguments
Applicant's arguments filed 8 Sep 2025 have been fully considered but they are not persuasive. Applicant argues that the claim amendments have overcome the previous rejections under 112b. While some of the previous rejections have been overcome, there are remaining issues of clarity as detailed in the rejections above. Regarding claims 27-30 and the previous 112a and 112b rejections, applicant argues that the specification describes a computer program for performing the claimed functions relating to the “program module”. However, as the claim invokes interpretation under 112f, the specification is required to describe and clearly link the claimed function to a particular structure. A computer program is not structure and the written description does not describe what a “program module” actually is, which makes the scope of the claim unclear. Applicant argues that a person of ordinary skill would possess the expertise to practice the claimed functions of the program module. However, the rejection under 112a is based on lack of written description rather than enablement. The fact that a person of ordinary skill could practice the claimed function does not satisfy the requirement under 112a for applicant to provide a written description of the structure for performing the claimed functions.
Regarding claim 16, applicant argues that Meyer only measures an outer surface of the crystal and thus does not scan the crystal “in volume” as claimed, when forming the 3D model. Examiner respectfully disagrees. As Meyer explicitly describes forming a 3 dimensional model of the crystal (p 12, lines 29-32), and any 3 dimensional object and model thereof inherently has a volume, this claimed step is satisfied by Meyer. Contrary to applicant’s arguments, there is no claim limitation requiring the recorded defects to be located in the interior of the crystal. Applicant argues that the scanning of Mitamura does not provide a fine spatial resolution of defect location. However, the claims require no particular resolution and do not define a particular defect type or location.
Applicant further argues that Mitamura does not teach the claimed regular slicing pitch configured to cut wafers of identical thickness. However, this limitation is taught by Meyer, which shows a regular slicing pitch in figures 13 and 14. Applicant argues that Mitamura teaches away from a regular slicing pitch based on figure 5. However, the changing of the cutting locations taught by Mitamura are dependent upon defect location. As shown in fig 3A of Mitamura which shows a regular cutting interval of 35cm, Mitamura is capable of performing cutting at regular intervals and thus does not teach away from regular cutting intervals. While Mitamura does disclose changing cutting locations to avoid internal defects, there is no teaching away from regular spacing, as Mitamura does not criticize or discredit a slicing machine with a regular slicing pitch, such as that disclosed by Meyer. The method of Mitamura can be used to avoid defects on the ends of the core without requiring an irregular pitch.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARCEL T DION/Examiner, Art Unit 3723
/BRIAN D KELLER/Supervisory Patent Examiner, Art Unit 3723