DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of national stage of a 371 of international application PCT/JP2022/023979 filed on 06/15/2022 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/06/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Preliminary Amendment
The preliminary amendment entered on 12/06/2024 with claim 4 amended. Claims 1-4 examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wang (US 20170192715).
Regarding Claim 1, Wang teaches
A robot control device comprising: (Wang [0003] a variety of embedded devices are popular in industrial applications and consumer electronics) (i.e., a robot control device in the preamble is intended use. Wang teaches embedded device and robot control device is an obvious variation of embedded device)
a processor; a non-volatile memory; and a volatile memory, (Wang [0008] the device comprises: a flash memory; the volatile RAM; and a processor)
wherein the processor secures, in the volatile memory, a cache memory area with a size equal to that of a predetermined area in the non-volatile memory, (Wang [0008] a processor that is used for allocating …memory … [0026] FIG. 1, a memory block is assigned in the volatile RAM so that the size of the assigned memory block equals to the size of the NVRAM to be emulated.)
and also writes data to the predetermined area in the non-volatile memory when writing the data to the cache memory area in the volatile memory by software control, (Wang FIG. 1, 3. Write [0052] API to read/write data from/into the RAM [0080] the teachings of the present disclosure are implemented as a combination of hardware and software) (i.e., from Fig. 1, 3. write, it shows that write data to volatile RAM also write to non-volatile NVRAM)
and reads data from the volatile memory when reading the data. (Wang Fig. 1, 2. read) (i.e., from Fig.1, 2. read, it shows that read data is from volatile RAM)
Regarding Claim 3, Wang teaches
A control method by a robot control device (Wang [0003] a variety of embedded devices are popular in industrial applications and consumer electronics) (i.e., a robot control device in the preamble is intended use. Wang teaches embedded device and robot control device is an obvious variation of embedded device)
including a processor, a volatile memory, and a non-volatile memory, comprising: (Wang [0008] the device comprises: a flash memory; the volatile RAM; and a processor)
a step of the processor securing, in the volatile memory, a cache memory area with a size equal to that of a predetermined area in the non-volatile memory; (Wang [0008] a processor that is used for allocating …memory … [0026] FIG. 1, a memory block is assigned in the volatile RAM so that the size of the assigned memory block equals to the size of the NVRAM to be emulated.)
and a step of the processor also writing data to the predetermined area in the non-volatile memory when writing the data to the cache memory area in the volatile memory by software control, (Wang FIG. 1, 3. Write [0052] API to read/write data from/into the RAM [0080] the teachings of the present disclosure are implemented as a combination of hardware and software) (i.e., from Fig. 1, 3. write, it shows that write data to volatile RAM also write to non-volatile NVRAM)
and reading data from the volatile memory when reading the data. (Wang Fig. 1, 2. read) (i.e., from Fig.1, 2. read, it shows that read data is from volatile RAM)
Regarding Claim 4, Wang teaches
A non-transitory computer readable medium having recorded thereon a program causing a processor of (Wang [0077] Non-transitory computer-readable medium comprising a computer program product recorded thereon and capable of being run by a processor, including program code instructions for implementing the steps of a method)
a robot control device (Wang [0003] a variety of embedded devices are popular in industrial applications and consumer electronics) (i.e., a robot control device in the preamble is intended use. Wang teaches embedded device and robot control device is an obvious variation of embedded device)
including a non-volatile memory and a volatile memory (Wang [0008] the device comprises: a flash memory; the volatile RAM; and a processor)
to secure, in the volatile memory, a cache memory area with a size equal to that of a predetermined area in the non-volatile memory, (Wang [0008] a processor that is used for allocating …memory … [0026] FIG. 1, a memory block is assigned in the volatile RAM so that the size of the assigned memory block equals to the size of the NVRAM to be emulated.)
and also write data to the predetermined area in the non-volatile memory when writing the data to the cache memory area in the volatile memory by software control, (Wang FIG. 1, 3. Write [0052] API to read/write data from/into the RAM [0080] the teachings of the present disclosure are implemented as a combination of hardware and software) (i.e., from Fig. 1, 3. write, it shows that write data to volatile RAM also write to non-volatile NVRAM)
and read data from the volatile memory when reading the data. (Wang Fig. 1, 2. read) (i.e., from Fig.1, 2. read, it shows that read data is from volatile RAM)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20170192715), in view of Kinoshita (US 20170060706).
Regarding Claim 2, Wang teaches
wherein the cache memory area in the volatile memory and the predetermined area in the non-volatile memory [are with equal size] (Wang [0026] FIG. 1, a memory block is assigned in the volatile RAM so that the size of the assigned memory block equals to the size of the NVRAM to be emulated.)
address space [of volatile memory] (Wang [0032] a continuous address space in the volatile RAM)
[update offset of non-volatile memory based on] offset from an address of the volatile memory (Wang [0034] the offset field indicates the address offset from a basic address of the volatile RAM [0056] updating the address offset of the update data region of the active memory zone)
Wang teaches volatile memory size equals non-volatile memory size (Wang [0026]) and address space of volatile memory (Wang [0032]), but Wang does not explicitly teach wherein the cache memory area in the volatile memory and the predetermined area in the non-volatile memory are address spaces in one-to-one correspondence, and the processor constantly derives a corresponding address of the non-volatile memory with a predetermined offset from an address of the volatile memory.
However, Kinoshita teaches address spaces in one-to-one correspondence (Kinoshita
[0122] the address space of the volatile memory 101 and the address space of the nonvolatile memory 104 correspond by one to one)
and the processor constantly derives a corresponding address of the non-volatile memory with a predetermined offset from an address of the volatile memory. (Kinoshita [0122] the NVDIMM controller 103 identifies the region of the nonvolatile memory 104 where the data of the application program has been saved, from the address data of the region of the volatile memory 101… the volatile data memory address data portion (DIMM address and offset) corresponding to the current index can be identified as the address data (nonvolatile data memory address) indicating the region (save region) of the nonvolatile memory 104 where the data of the corresponding application program has been saved.)
Wang and Kinoshita are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Wang and Kinoshita to modify Wang‘s emulated memory with Kinoshita’s teaching of address space of volatile memory and non-volatile memory correspond by one by one. The motivation for doing so would be able to identify address where data has been saved in volatile memory and non-volatile memory (Kinoshita [0122]).
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Shang (CN 121501692) teaches embedded device with processor creating uncache memory area.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEI MA whose telephone number is (571)272-2468. The examiner can normally be reached Monday through Friday from 8am to 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JARED RUTZ can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WEI MA/Examiner, Art Unit 2135
Prosecution Insights