Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other References – Cheon US 20100262765 - 0005- n SRAM, a flash memory, a flash EEPROM, 0126 Referring to FIG. 24A, the physical memory space (or RPS) can be formed with two data areas A and B and a spare area. The data area may be a semiconductor memory chip or a block unit of the semiconductor chip or a minimum unit to perform an erasing operation in a NAND flash memory
Allowable Subject Matter
Claims 15, 26-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (subject to overcoming any rejections in this office action.).
REASONS FOR ALLOWANCE
The following is an examiner’s statement of reasons for allowance:
For Claim 15, while the prior art renders obvious the limitations from base claims 13, the prior art does not teach the limitations from Claim 15, when viewed in combination with the other recited limitations.
For Claim 26, while the prior art renders obvious the limitations from base claim 23, the prior art does not teach the limitations from Claim 26, when viewed in combination with the other recited limitations.
Claims 27-30, 31, 32 are allowable based on dependency from Claim 26.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13, 20, 22, 23, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Yamagami (US 20010030890) in view of Sinclair (20050251617) and further in view of Gorobets (US 20070101095 A1) and Virani (US 11042481)
Claim 13. Yamagami discloses A data writing method based on a simulated electrically erasable programmable read-only memory (EEPROM) (eg., 0011 flash memory has been known as one sort of EEPROM.; [0048] writing file data has been received from the host bus 3. FIG. 4 illustrates the processing steps of a write process which is executed by the microcomputer 4.),
wherein the simulated EEPROM comprises a static random access memory (eg., 0045 - buffer memory 6 is a memory in which data to be written into the data memory 8 and the error memory 7 or data read out of them are temporarily stored, and which is constructed of an SRAM ) and
a flash, the flash comprises at least two storage groups, the at least two storage groups comprise a first storage group and a second storage group; the data writing method based on the simulated EEPROM comprises: (eg., 0045 – Fig. 1 - data memory 8 is constructed of sixteen flash memory elements of 2 MB each.)
writing to-be-written data into a target address of the static random access memory (eg., 0055 - Data delivered from the host bus 3 are latched into the buffer memory 6 at the step 400 …. At the next step 403, the data to-be-written latched in the buffer memory 6 are written into that block of the data memory 8 which is expressed by the physical address calculated at the step 402.); and
writing the to-be-written data into the first storage group in a preset writing order (eg., 0055 - At the next step 403, the data to-be-written latched in the buffer memory 6 are written into that block of the data memory 8 which is expressed by the physical address calculated at the step 402), and
Yamagami does not disclose, but Sinclair discloses
determining whether the first storage group is in a full storage state; when the first storage group is in the full storage state, writing the to-be-written data into the second storage group in the preset writing order (eg., [0118] a system would end up with the sort of order shown in FIG. 10 … the blocks were written in the order received in a single plane until it were filled, and then moving on to the next plane and repeating the process; 0010 - Flash memories are particularly suited to the storage of large amounts of logically continuous host data).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, providing the benefit of a memory system having a controller portion and a memory portion, where the memory portion for the storage of user data is based on a flash EEPROM technology and the controller includes a non-volatile memory from another non-volatile technology (see Sinclair, 0027).
Yamagami in view of Sinclair does not disclose, but Gorobets discloses
and erasing the to-be-written data in the first storage group (eg., 0054 - The erased block manager 160 manages the erase operation of the metablocks and their allocation for storage of new information).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets, providing the benefit of memory system having multiple erase blocks in multiple planes, a selected number of erase blocks are programmed together as an adaptive metablock. The number of erase blocks in an adaptive metablock is chosen according to the data to be programmed (see Gorobets, 0019).
Yamagami in view of Sinclair and Gorobets does not disclose, but Virani discloses
wherein the method further comprises: packaging the to-be-written data, the target address and additional information, to generate a to-be-verified data packet, wherein the additional information comprises a valid flag bit; the valid flag bit is used to determine whether the to-be-verified data packet is valid (eg., col 2:5-16 - data to be written, as specified by a host request. A host request can include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location the host system associates with the host data. The logical address information (e.g., LBA, namespace) can be part of metadata for the host data. Metadata can also include error handling data (e.g., ECC codeword, parity code), data version (e.g. used to distinguish age of data written), valid bitmap (which LBAs or logical transfer units contain valid data) ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets with Virani, providing the benefit of efficient processing of commands in memory sub-systems (see Virani, col 1:48-50) a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices (col 1:15-17).
Claim 20. Yamagami in view of Sinclair does not disclose, but Gorobets discloses
The data writing method based on the simulated EEPROM according to The data writing method based on the simulated EEPROM according to wherein the preset writing order is an order from top to bottom (eg., 0038 - FIG. 3A(i) shows the data from a logical group LG.sub.i, where the logical sectors are in contiguous logical order 0, 1, . . . , N-1. FIG. 3A(ii) shows the same data being stored in the metablock in the same logical order. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets, providing the benefit of memory system having multiple erase blocks in multiple planes, a selected number of erase blocks are programmed together as an adaptive metablock. The number of erase blocks in an adaptive metablock is chosen according to the data to be programmed (see Gorobets, 0019).
Claim 22. Yamagami discloses The data writing method based on the simulated EEPROM according to The data writing method based on the simulated EEPROM according to wherein a last row of a respective storage group of the storage groups is used to store the number of erasures of the flash (eg., 0082 - A number of erasures management table (number of erasures reference means) 27 registers the cumulative numbers of erasures of a respective physical addresses. A status table (status reference means) 28 is for referring to the statuses of the respective physical sectors. A write buffer 29 serves to temporarily store data to-be-written therein)
Claim 23. Yamagami discloses A data management method based on a simulated electrically erasable programmable read-only memory (EEPROM), the data management method based on the simulated EEPROM comprises:
(eg., 0011 flash memory has been known as one sort of EEPROM.; [0048] writing file data has been received from the host bus 3. FIG. 4 illustrates the processing steps of a write process which is executed by the microcomputer 4.),
wherein the simulated EEPROM comprises a static random access memory (eg., 0045 - buffer memory 6 is a memory in which data to be written into the data memory 8 and the error memory 7 or data read out of them are temporarily stored, and which is constructed of an SRAM ) and
a flash, the flash comprises at least two storage groups, the at least two storage groups comprise a first storage group and a second storage group (eg., 0045 – Fig. 1 - data memory 8 is constructed of sixteen flash memory elements of 2 MB each.)
writing EEPROM data according to a data writing method based on the simulated EEPROM (eg., [0048] Next, let's consider a case where an instruction for writing file data has been received from the host bus 3. FIG. 4 illustrates the processing steps of a write process which is executed by the microcomputer 4);
reading the EEPROM data according to a data reading method based on the simulated EEPROM (eg., 0048 - the read operation );
writing to-be-written data into a target address of the static random access memory (eg., 0055 - Data delivered from the host bus 3 are latched into the buffer memory 6 at the step 400 …. At the next step 403, the data to-be-written latched in the buffer memory 6 are written into that block of the data memory 8 which is expressed by the physical address calculated at the step 402.); and
writing the to-be-written data into the first storage group in a preset writing order (eg., 0055 - At the next step 403, the data to-be-written latched in the buffer memory 6 are written into that block of the data memory 8 which is expressed by the physical address calculated at the step 402), and
Yamagami does not disclose, but Sinclair discloses
writing the to-be-written data into the first storage group in a preset writing order, and determining whether the first storage group is in a full storage state; when the first storage group is in the full storage state, writing the to-be-written data into the second storage group in the preset writing order (eg., [0118] a system would end up with the sort of order shown in FIG. 10 … the blocks were written in the order received in a single plane until it were filled, and then moving on to the next plane and repeating the process; 0010 - Flash memories are particularly suited to the storage of large amounts of logically continuous host data).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, providing the benefit of a memory system having a controller portion and a memory portion, where the memory portion for the storage of user data is based on a flash EEPROM technology and the controller includes a non-volatile memory from another non-volatile technology (see Sinclair, 0027).
Yamagami in view of Sinclair does not disclose, but Gorobets discloses
erasing the to-be-written data in the first storage group (eg., 0054 - The erased block manager 160 manages the erase operation of the metablocks and their allocation for storage of new information).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets, providing the benefit of memory system having multiple erase blocks in multiple planes, a selected number of erase blocks are programmed together as an adaptive metablock. The number of erase blocks in an adaptive metablock is chosen according to the data to be programmed (see Gorobets, 0019).
Yamagami in view of Sinclair and Gorobets does not disclose, but Virani discloses
wherein the method further comprises: packaging the to-be-written data, the target address and additional information, to generate a to-be-verified data packet, wherein the additional information comprises a valid flag bit; the valid flag bit is used to determine whether the to-be-verified data packet is valid (eg., col 2:5-16 - data to be written, as specified by a host request. A host request can include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location the host system associates with the host data. The logical address information (e.g., LBA, namespace) can be part of metadata for the host data. Metadata can also include error handling data (e.g., ECC codeword, parity code), data version (e.g. used to distinguish age of data written), valid bitmap (which LBAs or logical transfer units contain valid data) ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets with Virani, providing the benefit of efficient processing of commands in memory sub-systems (see Virani, col 1:48-50) a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices (col 1:15-17).
Claim 25. Yamagami discloses A data management system based on a simulated electrically erasable programmable read-only memory (EEPROM); the processor is configured to execute the data management method based on the simulated EEPROM according to claim 23 (eg., 0011 flash memory has been known as one sort of EEPROM.; [0048] writing file data has been received from the host bus 3. FIG. 4 illustrates the processing steps of a write process which is executed by the microcomputer 4.), comprising:
a processor (eg., a memory controller ),
a flash (eg., 0045 - data memory 8 )and
a static random access memory (eg., 0045 - buffer memory 6),
wherein the flash comprises a plurality of storage groups; and (eg., 0045 – Fig. 1 - data memory 8 is constructed of sixteen flash memory elements of 2 MB each.).
Claim 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamagami (US 20010030890) in view of Sinclair (20050251617) and further in view of Gorobets (US 20070101095 A1) and Virani (cited above) and Lee (US 20080098164 A1)
Claim 16. Yamagami in view of Sinclair and Gorobets and Virani does not disclose, but Lee discloses
The data writing method based on the simulated EEPROM according to The data writing method based on the simulated EEPROM according to wherein an additional bit added to an original bit width of the static random access memory is used as the valid flag bit (eg., 0052 Fig. 7A When the address matches, and a valid bit indicates that the cached data is valid, ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets, and Virani with Lee, providing the benefit of [0056] When the address matches, step 450, then the host data is written to the data portion of the cache in the SRAM buffer (see Lee, 0056).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yamagami (US 20010030890) in view of Sinclair (20050251617) and further in view of Gorobets (US 20070101095 A1) and Virani (cited above) and Borchers (US 20100269015 A1)
Claim 17. Yamagami in view of Sinclair, Gorobets and Virani does not disclose, but Borchers discloses
The data writing method based on the simulated EEPROM according to The data writing method based on the simulated EEPROM according to further comprising performing an error correcting code (ECC) operation on the to-be- verified data packet (eg., [0118] The controller 110 receives the verify on write command then writes the data to one of the memory devices. As the data is written to the memory device an error correction code is generated and associated with the written data. Then, the controller reads the data from the memory device and checks the ECC. The data is read back without sending the data back to the host ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets and Virani with Borchers providing the benefit of execute commands received from a host on the data storage device while minimizing the processing impact and overhead on the host and the data storage device (see Borchers, 0005).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yamagami (US 20010030890) in view of Sinclair (20050251617) and further in view of Gorobets (US 20070101095 A1), and Virani (cited above) and Liang (US 10228868 B1)
Claim 18. Yamagami in view of Sinclair Gorobets and Virani does not disclose, but Liang disclosed
The data writing method based on the simulated EEPROM according to The data writing method based on the simulated EEPROM according to wherein the depth of the respective storage group of the storage groups is twice as the depth of the static random access memory (eg., col 12:10-15 - FIG. 1, for example, if the flash memory has a size of 100 GB and credit is based on a daily window, the client 112 may be allocated a client cache 124 of 50 GB,).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets and Virani, with Liang providing the benefit of systems and methods for managing a lifespan of a flash memory such as a solid state drive or a collection of solid state drives. Because the lifespan of flash memory is often expressed in terms of overwrites, the lifespan of the flash memory can be managed by tracking and potentially controlling writes that are made to the flash memory in a given period of time (see Liang, col 2:10-17).
Claims 19, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Yamagami (US 20010030890) in view of Sinclair (20050251617) and further in view of Gorobets (US 20070101095 A1) and and Virani (cited above), and further in view of and Merry (US 20080189452 A1)
Claim 19. Yamagami in view of Sinclair Gorobets and Virani does not disclose, but Merry disclosed
The data writing method based on the simulated EEPROM according to The data writing method based on the simulated EEPROM according to wherein the at least two storage groups comprise a head storage group, at least one middle storage group and a tail storage group; when the first storage group is the head storage group or the middle storage group, the second storage group is a next storage group adjacent to the first storage group; when the first storage group is the tail storage group, the second storage group is the head storage group (eg., [0026] The controller 114 preferably writes data to the blocks 137, and moves data from the blocks, in a circular fashion.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets and Virani with Merry, providing the benefit of [0019] During a write operation, the controller 114 initially writes the data received from the host 110 to the buffer memory 126, and then moves this data from the buffer memory 126 to the non-volatile storage (see Merry, 0019).
Claim 24 is rejected for reasons similar to Claim 19 above.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yamagami (US 20010030890) in view of Sinclair (20050251617) and further in view of Gorobets (US 20070101095 A1), and Virani (cited above) and Liang (US 10228868 B1)
Claim 21. Yamagami in view of Sinclair Gorobets and Virani does not disclose, but Liang disclosed
The data writing method based on the simulated EEPROM according to The data writing method based on the simulated EEPROM according to wherein a depth of a respective storage group of the storage groups is greater than or equal to a depth of the static random access memory. (eg., col 12:10-15 - Referring to FIG. 1, for example, if the flash memory has a size of 100 GB and credit is based on a daily window, the client 112 may be allocated a client cache 124 of 50 GB, the client 116 may be allocated a client cache of 25 GB, and the client 120 may be allocated a client cache 128 of 25 GB. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets, and Virani with Liang providing the benefit of systems and methods for managing a lifespan of a flash memory such as a solid state drive or a collection of solid state drives. Because the lifespan of flash memory is often expressed in terms of overwrites, the lifespan of the flash memory can be managed by tracking and potentially controlling writes that are made to the flash memory in a given period of time (see Liang, col 2:10-17).
Claims 33 is rejected under 35 U.S.C. 103 as being unpatentable over Yamagami (US 20010030890) in view of Sinclair (20050251617) and further in view of Gorobets (US 20070101095 A1) Kikuchi (US 20060143365) and Virani (cited above) and further in view of Ishikawa (US 20010037437)
Claim 33. Yamagami in view of Sinclair, Gorobets and Virani does not disclose, but Ishikawa disclosed
The data writing method based on the simulated EEPROM according to The data writing method based on the simulated EEPROM according to wherein the valid flag bit being valid indicates that the to-be-written data in the to-be-verified data packet is EEPROM data (eg., 0108 - two bits to the left of the DL field are made invalid, and the one bit next to the two invalid bits constitutes an IF field for storing bit data indicating which of the firmware flash EEPROM 56 and the I/O flash EEPROM 57 is to be selected as a target of access. The next 12 bits constitute a DSB field for storing data indicating an access end block address of the firmware flash EEPROM 56 or the I/O flash EEPROM 57 where data is transferred.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets, and Virani with Ishikawa providing the benefit an information processing device for executing a predetermined process in accordance with a program (see Ishikawa, 0046 – 0047).
Response to Arguments
Applicant's arguments filed 3/17/2026 have been fully considered but they are not persuasive.
For claims 1, and 23, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Yamagami in view of Sinclair and Gorobets and Kicuchi does not disclose, but Virani discloses
wherein the method further comprises: packaging the to-be-written data, the target address and additional information, to generate a to-be-verified data packet, wherein the additional information comprises a valid flag bit; the valid flag bit is used to determine whether the to-be-verified data packet is valid (eg., col 2:5-16 - data to be written, as specified by a host request. A host request can include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location the host system associates with the host data. The logical address information (e.g., LBA, namespace) can be part of metadata for the host data. Metadata can also include error handling data (e.g., ECC codeword, parity code), data version (e.g. used to distinguish age of data written), valid bitmap (which LBAs or logical transfer units contain valid data) ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the writing to-be-written data in a buffer and flash memory as disclosed by Yamagami, with Sinclair, with Gorobets and Kicuchi with Virani, providing the benefit of efficient processing of commands in memory sub-systems (see Virani, col 1:48-50) a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices (col 1:15-17).
New Claim 33 is rejected above.
Applicant’s arguments for dependent claims 15-22, 33 and 24-32 are based on their respective base independent claims 1 and 23, which are addressed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GAUTAM SAIN/Primary Examiner, Art Unit 2135
Prosecution Insights