Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to application filed 03/20/2026.
Claims 1-9 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/09/2024 has been placed in record and considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (US 2012/0047502 A1) in view of Nuthakki et al. (US 11,720,254 B2)
Regarding claim 1, Hashimoto discloses an information processing apparatus capable of executing an application of any one of a container and a virtual machine ([0045]: The logical units as virtual disks 225 are divided into a group of logical units 231 for the virtual storage system (0) and a group of logical units 241 for the virtual storage system (1). The virtual storage system (0) is accessed by the virtual computer (0) 131 and the virtual storage system (1) is accessed by the virtual computer (1) 141), the apparatus comprising:
a CPU; a connection interface (IF)for connecting a plurality of devices to the CPU ([0036]: The I/O bus 113 connects the CPU 111 and the I/ O adaptors 114 and 115 to exchange data. The I/O adaptor 114 is connected with the storage system 200 through an I/O channel (for example, Fiber Channel) 400 and transmits a request for data input/output to the storage system 200 and receives data stored in the storage system 200. The I/O adaptor 115 is connected with the control terminal 300 through a network 410);
wherein in the bandwidth, a logical resource amount is defined and an allocation proportion associated with the device is set based on the logical resource amount ([0141]: the storage hypervisor 220 makes allocation of the bandwidth of the internal network 1104 between the virtual computer (0) 131 and virtual computer (1) 141 and the control processor 212 processes input and output according to the allocation. [0149]: The table shown in FIG. 17 contains a “bandwidth of internal network” column 1300 as an additional column. This column is used to specify the allocation rate of the bandwidth of the internal network 1104 for each of the virtual computer (0) 131 and virtual computer (1) 141), and
the adjustment unit is configured to perform control such that the bandwidth usage is reduced for a case where a usage proportion of the bandwidth is higher than an allocation proportion ([0149]: the allocation rate is expressed as a percentage to the overall bandwidth. The control processor 212 monitors the internal network bandwidth used by the virtual computer (0) 131 and virtual computer (1) 141, and delays input/output processes as necessary to prevent the internal network bandwidth from exceeding a preset level).
However, Hashimoto does not disclose a monitoring unit configured to monitor whether a bandwidth usage of the connection IF exceeds an upper limit; and an adjustment unit configured to adjust the bandwidth usage in a case where the usage exceeds the upper limit.
In an analogous art, Nuthakki discloses a monitoring unit configured to monitor whether a bandwidth usage of the connection IF exceeds an upper limit; and an adjustment unit configured to adjust the bandwidth usage in a case where the usage exceeds the upper limit (fig. 11, [0122]: determined whether the current cumulative bandwidth consumption rate exceeds the BWT. If the BWT is not exceeded, the method may proceed to a step 1118. Otherwise, in a step 1116, a bandwidth adjustment may be made to one of the I/O connections to reduce the cumulative bandwidth consumption rate below the BWT for the physical host port).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Hashimoto to comprise “monitoring unit configured to monitor whether a bandwidth usage of the connection IF exceeds an upper limit; and an adjustment unit configured to adjust the bandwidth usage in a case where the usage exceeds the upper limit” taught by Nuthakki.
One of ordinary skilled in the art would have been motivated because it would have enabled to managing I/O bandwidth limits for I/O connections involving virtual host ports (Nuthakki, [0001]).
Regarding claim 2, Hashimoto-Nuthakki discloses the information processing apparatus according to claim 1, wherein the device is a first device capable of adjusting the bandwidth usage of the connection IF by changing the setting of the device, and the adjustment unit is configured to perform control to reduce the available bandwidth in a case where the usage exceeds an upper limit (Nuthakki, fig. 11, [0122]: determined whether the current cumulative bandwidth consumption rate exceeds the BWT. If the BWT is not exceeded, the method may proceed to a step 1118. Otherwise, in a step 1116, a bandwidth adjustment may be made to one of the I/O connections to reduce the cumulative bandwidth consumption rate below the BWT for the physical host port). The same rationale applies as in claim 1.
Regarding claims 5 and 6; the claims are interpreted and rejected for the same reason as set forth in claim 1.
Regarding claim 7; the claim is interpreted and rejected for the same reason as set forth in claim 2.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable Hashimoto in view of Nuthakki as applies to claim 1, in further view of Aoki (US WO 2016/092604 A1).
Regarding claim 3, Hashimoto-Nuthakki discloses the information processing apparatus according to claim 1, wherein the device is a second device capable of adjusting the bandwidth usage of the connection IF by controlling a throughput of the device (Nuthakki, [0024]: each host port of a host that is physically connected to an SHP, the host may negotiate (e.g. controlling) a maximum bandwidth threshold (BWT; i.e., the maximum throughput) for the physical link between the host port and the SHP (i.e., fabric port) to which the host port is connected by the link. fig. 11, [0122]: determined whether the current cumulative bandwidth consumption rate exceeds the BWT…a bandwidth adjustment may be made to one of the I/O connections to reduce the cumulative bandwidth consumption rate below the BWT for the physical host port).
However, Hashimoto-Nuthakki does not disclose the adjustment unit is configured to perform one of a control to reduce the number of arithmetic units and a control to lower an operating clock in a case where the usage exceeds an upper limit.
In an analogous art, Aoki discloses the adjustment unit is configured to perform one of a control to reduce the number of arithmetic units and a control to lower an operating clock in a case where the usage exceeds an upper limit (pg. 13, [0002]: Change allocation by increasing / decreasing the number of cores to be executed. When changing the disk I / O resources, the resource assignment unit 320 changes the reserved bandwidth to the I / O device used by the container. The same band change is made also for the network).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Hashimoto-Nuthakki to comprise “the adjustment unit is configured to perform one of a control to reduce the number of arithmetic units and a control to lower an operating clock in a case where the usage exceeds an upper limit” taught by Aoki.
One of ordinary skilled in the art would have been motivated because it would have enabled to adjust the I/O bandwidth of the virtual device by changing the number of cores to be executed (Aoki, pg. 13, [0002]).
Regarding claim 8; the claim is interpreted and rejected for the same reason as set forth in claim 3.
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto in view of Nuthakki, as applied to claim 3, in view of Mahindru et al. (US 2018/0101214 A1) in further view of Shima et al. (US 9,515,887 B2).
Regarding claim 4, Hashimoto-Nuthakki discloses the information processing apparatus according to claim 3.
However, Hashimoto-Nuthakki does not wherein a minimum change width of a change in arithmetic performance due to control for reducing the number of arithmetic units is different from a minimum change width of a change in arithmetic performance due to control for lowering the operation clock, and a value at which a change amount in a case where a setting value having a smaller minimum change width is lowered is equal to a change amount in a case where a setting value having a larger minimum change width is lowered is set as a threshold value, priority setting in which priority is registered between control for reducing the number of arithmetic units and control for lowering the operation clock is performed.
In an analogous art, Mahindru discloses wherein a minimum change width of a change in arithmetic performance due to control for reducing the number of arithmetic units is different from a minimum change width of a change in arithmetic performance due to control for lowering the operation clock, and a value at which a change amount in a case where a setting value having a smaller minimum change width is lowered is equal to a change amount in a case where a setting value having a larger minimum change width is lowered is set as a threshold value ([0025]: re-adjusting the clock speeds and voltages at which processing cores (and hence, circuits, transistors clock frequency) operate. Throughput is different than performance, as it is possible to achieve higher performance per thread or core but with much more power used relatively, versus using more cores with lower performance (i.e. lower clock speed) but less power per core to achieve higher overall throughput), priority setting in which priority is registered between control for reducing the number of arithmetic units and control for lowering the operation clock is performed ([0067]: if a High priority workload generally requires a lower level of its allowed range for clock speed, then it may be re-categorized as a Medium priority workload, and so on. Additionally, power may be assigned to certain workloads based on demand in order to increase performance (clock speed) of the processor/processor core by lowering the power and hence, clock speed of other, lower priority or lower demand workloads).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Hashimoto-Nuthakki to comprise “wherein a minimum change width of a change in arithmetic performance due to control for reducing the number of arithmetic units is different from a minimum change width of a change in arithmetic performance due to control for lowering the operation clock, and a value at which a change amount in a case where a setting value having a smaller minimum change width is lowered is equal to a change amount in a case where a setting value having a larger minimum change width is lowered is set as a threshold value, priority setting in which priority is registered between control for reducing the number of arithmetic units and control for lowering the operation clock is performed” taught by Mahindru.
One of ordinary skilled in the art would have been motivated because it would have enabled adjusting the voltage and the clock speed of respective processor cores within the set of processor cores according to a workload priority of respective workloads performed by each respective one of the processor core (Mahindru, [0006]).
However, Hashimoto-Nuthakki-Mahindru does not disclose the adjustment unit is configured to gradually decrease the setting value having a smaller minimum change width in a case where the usage amount exceeds an upper limit, and then in a case where the smaller minimum change width reaches the threshold value by decreasing the set value, decrease the set value of the value that has been prioritized and returns the other set value to the initial state.
In an analogous art, Shima discloses the adjustment unit is configured to gradually decrease the setting value having a smaller minimum change width in a case where the usage amount exceeds an upper limit, and then in a case where the smaller minimum change width reaches the threshold value by decreasing the set value, decrease the set value of the value that has been prioritized and returns the other set value to the initial state (column 11, 36-47: When the actual band of the socket C becomes 1 Mbps, the lower limit network band lower_bps for the priorities higher than the priority 31 of the socket A of interest is 40 Mbps, and the present consumed band current_priority_bps for the priority 31 of the socket A of interest is 60 Mbps. Thus, the necessary band needed is 40 Mbps+60 Mbps=100 Mbps. The band shortage is 100 Mbps−60 Mbps=40 Mbps. It is determined that there is a band shortage. Because of the band shortage, the socket A is subjected to band control. As a result, as shown in FIG. 6B, the actual band of the socket A gradually decreases to 20 Mbps, whereas the actual band of the socket C gradually increases and reaches 40 Mbps).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Hashimoto-Nuthakki-Mahindru to comprise “the adjustment unit is configured to gradually decrease the setting value having a smaller minimum change width in a case where the usage amount exceeds an upper limit, and then in a case where the smaller minimum change width reaches the threshold value by decreasing the set value, decrease the set value of the value that has been prioritized and returns the other set value to the initial state” taught by Shima.
One of ordinary skilled in the art would have been motivated because it would have enabled to appropriately allocate a network band to a plurality of communications (Shima, column 1, 43-44).
Regarding claim 9; the claim is interpreted and rejected for the same reason as set forth in claim 4.
Additional References
The prior art made of record and not relied upon is considered pertinent to applicants disclosure.
Mithal et al., US 10,630,554 B1: Input/Output (I/O) Performance of Host Through Bi-Directional Bandwidth Feedback Optimization.
Depew et al., US 2018/0165238 A1: Self-Tune Controller.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUAN C TURRIATE GASTULO whose telephone number is (571)272-6707. The examiner can normally be reached Monday - Friday 8 am-4 pm.
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/J.C.T/Examiner, Art Unit 2446
/BRIAN J. GILLIS/Supervisory Patent Examiner, Art Unit 2446
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