Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because it exceeds 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2008/0178924 to Kempa.
Regarding claims 1-4, Kempa teaches a semiconductor device (Fig. 4A) comprising
A first semiconductor element 1B including a semiconductor layer 7B and a first bonding surface (such as bottom surface of 17B; ¶0044, 0045)
A second semiconductor element 1A having a second bonding surface (such as top surface of 5A) facing the first bonding surface
A plurality of electrically-conductive nanoparticles 3 positioned between the first bonding surface and the second bonding surface and electrically connecting the first semiconductor element 1B and the second semiconductor element 1A to each other (Fig. 4B, ¶0016)
Wherein the plurality of electrically-conductive nanoparticles 3 intrude into the semiconductor layer 7B (best seen in Fig. 5F).
Kempa discusses embodiments in which the material of a semiconductor layer such as 7B is silicon (¶0014, 0015, 0033). Therefore a person having ordinary skill in the art would at once envisage an embodiment in which the semiconductor layer is a silicon layer. A reference disclosure can anticipate a claim even if the reference does not describe "the limitations arranged or combined as in the claim, if a person of skill in the art, reading the reference, would ‘at once envisage’ the claimed arrangement or combination." Kennametal, Inc. v. Ingersoll Cutting Tool Co., 780 F.3d 1376, 1381, 114 USPQ2d 1250, 1254 (Fed. Cir. 2015), MPEP §2131.02.III.
Per claim 2, Kempa teaches the limitations of claim 1. Each of the plurality of electrically-conductive nanoparticles 3 contains one of copper, gold, or palladium (¶0016).
Per claim 3, Kempa teaches the limitations of claim 1. An exposure height of the plurality of electrically-conductive nanoparticles is 0 nm, as all of each nanoparticle is entirely covered (Fig. 4A). An intrusion height into the silicon layer 7B is more than 5 nm (¶0015).
Per claim 4, Kempa teaches the limitations of claim 1. The silicon layer 7B of the first semiconductor element 1B contains crystalline silicon or amorphous silicon (¶0033). The second semiconductor element 1A contains an organic-based material in an embodiment (¶0026).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0315201 to Lin, and further in view of US 2018/0019122 to Guiton. Supporting information regarding terms of the art and physical properties is provided by US 2005/0016578 to Enomoto.
Regarding claims 5-10, Lin teaches a method of manufacturing a semiconductor device comprising steps of
Preparing a first semiconductor element including a silicon layer 21 (Fig. 6A, ¶0040) and having a first bonding surface (surface of 21, 22 facing top of page)
Preparing a second semiconductor element (Fig. 6B; 25 is a conducting polymer identified as PEDOT:PSS in ¶0037; PEDOT-PSS identified as a hole conducting polymer which forms a heterojunction in ¶0011; ¶0130 of Enomoto clarifies that PEDOT:PSS is a p-type semiconductor) having a bonding surface (portion of 25 facing top of page)
Facing and pressing the second bonding surface to and against the first bonding surface (Fig. 6C).
The first bonding surface of the first semiconductor element is collectively formed by silicon nanostructures, which may be formed by vapor or liquid based methods (¶0037). Lin does not teach the claimed step (c), the claimed step (d) performed after step (c). Guiton teaches that silicon nanostructures (¶0027) can also be formed a step (c) of arranging a plurality of electrically-conductive nanoparticles (“nanodroplets” in the text) on the first bonding surface (Fig. 1, ¶0026-0029), followed by a step of (d) intruding the plurality of electrically-conductive nanoparticles into the silicon layer (¶0031-0033), resulting in silicon nanostructures that are high quality and highly organized (¶0023). Therefore it would have been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in the art to include a step similar to claimed step (c), and a step similar to claim (d) after step (c), in order to produce high quality, highly organized nanostructures. The step (e) would necessarily follow after step (d) in the method of modified-Lin, such that the facing and pressing the second bonding surface to and against the first bonding surface occurs through the plurality of electrically-conductive nanoparticles therebetween.
Per claim 6, modified-Lin teaches the limitations of claim 5. According to Guiton, the particles are made of copper (¶0029).
Per claim 7, modified-Lin teaches the limitations of claim 5. According to Guiton, it would have been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in the art to vary the intrusion height into the silicon layer in order to determine the properties of the silicon nanostructures (¶0040).
According to Guiton, the electrically conductive nanoparticles are formed at the end of the silicon nanostructures. According to Lin, it would have been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in the art to adjust the degree of exposure of the silicon nanostructures by varying a pressing force in order to make sure the nanostructures are structurally supported and adhered (¶0038-0040).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). The discovery of an optimum value of a known result effective variable, without producing any new or unexpected results, is within the ambit of a person of ordinary skill in the art. See In re Boesch, 205 USPQ 215 (CCPA 1980) (see MPEP § 2144.05, II.).
As such, the exposure height of the plurality of electrically-conductive nanoparticles is an obvious result of the optimization of adherence and structural support of the silicon nanostructures.
Per claim 8, modified-Lin teaches the limitations of claim 5. A semiconductor material made of crystalline silicon or amorphous silicon is used as the silicon layer of the first semiconductor element (¶0028 of Lin, ¶0023 of Guiton). The second semiconductor element is made of an organic-based material (PEDOT:PSS, see cited passages above).
Per claims 9 and 10, modified-Lin teaches the limitations of claims 5 and 8. In step (d), the plurality of electrically-conductive nanoparticles are intruded into the silicon layer by a metal assisted chemical etching method (solid-liquid-vapor etching, ¶0023, 0026, 0027).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2016/0043241.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan S Cannon whose telephone number is (571)270-7186. The examiner can normally be reached M-F, 8:30am-5:30pm PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Barton can be reached at (571) 272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Ryan S. Cannon
Primary Examiner
Art Unit 1726
/RYAN S CANNON/ Primary Examiner, Art Unit 1726