DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The objection to the specification is withdrawn due to Applicant’s amendment.
The previous art rejections of claims 1-4 are withdrawn due to Applicant’s amendment.
The previous art rejections of claims 5-8 are revised to incorporate new claim limitations.
New analysis follows.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2010/0288352 to Ji.
Regarding claims 1 and 2, Ji teaches a semiconductor device (Fig. 3) comprising
A first semiconductor element 105 including a silicon layer and having a first bonding surface (facing away from light 100, ¶0057, 0059)
A second semiconductor element 106 having a second bonding surface (facing toward light 100) facing the bonding surface
A plurality of electrically-conductive nanoparticles 132 (features 132 are nanoparticles in an embodiment, ¶0060-0062) positioned between the first bonding surface and the second bonding surface and electrically connecting the first semiconductor element 105 and the second semiconductor element 106 to each other
Wherein a portion of each of the plurality of electrically-conductive nanoparticles 132 intrudes into the silicon layer
Wherein the plurality of electrically conductive nanoparticles 132 do not intrude into the second semiconductor element 106.
Per claim 2, Ji teaches the limitations of claim 1. Each of the plurality of electrically-conductive nanoparticles 132 contains silver, gold, aluminum, nickel, zinc, or indium oxide (¶0061).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji as applied to claim 1 above.
Regarding claim 3, Ji teaches the limitations of claim 1. As the plurality of electrically-conductive nanoparticles 132 are fully embedded into the silicon layer of the first semiconductor element 105, an exposure height of the nanoparticles is 0 nm (Fig. 3). Ji is clear that the size of the plurality of electrically-conductive nanoparticles 132 is a result effective variable that would have been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in the art to vary in order to achieve the plasmonic function (¶0062).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). The discovery of an optimum value of a known result effective variable, without producing any new or unexpected results, is within the ambit of a person of ordinary skill in the art. See In re Boesch, 205 USPQ 215 (CCPA 1980) (see MPEP § 2144.05, II.).
As such, the intrusion height into the silicon layer depends from the size and scale of the plurality of electrically-conductive nanoparticles, and is an obvious result of optimization.
Regarding claim 4, Ji teaches the limitations of claim 1. The silicon layer of the first semiconductor element 105 contains amorphous silicon (¶0057), and it would have been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in the art to form the second semiconductor element to contain a chalcogenide (CIGS) in order to absorb the desired range of light wavelengths.
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0315201 to Lin (of record), and further in view of US 2018/0019122 to Guiton (of record). Supporting information regarding terms of art and physical properties is provided by US 2005/0016578 to Enomoto (of record).
Regarding claims 5-8, Lin teaches a method of manufacturing a semiconductor device comprising steps of
a) Preparing a first semiconductor element including a silicon layer 21 (Fig. 6A, ¶0040) and having a first bonding surface (surface of 21, 22 facing top of page)
b) Preparing a second semiconductor element (Fig. 6B; 25 is a conducting polymer identified as
PEDOT:PSS in ¶0037; PEDOT-PSS identified as a hole conducting polymer which forms a
heterojunction in ¶0011; ¶0130 of Enomoto clarifies that PEDOT:PSS is a p-type semiconductor)
having a bonding surface (portion of 25 facing top of page)
e) Facing and pressing the second bonding surface to and against the first bonding surface (Fig.
6C).
The first bonding surface of the first semiconductor element is collectively formed by silicon
nanostructures, which may be formed by vapor or liquid based methods (¶0037). Lin does not teach the
claimed step (c), the claimed step (d) performed after step (c). Guiton teaches that silicon
nanostructures (¶0027) can also be formed a step (c) of arranging a plurality of electrically-conductive
nanoparticles ("nanodroplets" in the text) on the first bonding surface (Fig. 1, ¶0026-0029), followed by
a step of (d) intruding a (whole) portion of each of the plurality of electrically-conductive nanoparticles into the silicon layer (¶0031-0033), resulting in silicon nanostructures that are high quality and highly organized (¶0023). Therefore it would have been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in the art to include a step similar to claimed step (c), and a step similar to claim (d) after step (c), in order to produce high quality, highly organized nanostructures. The step (e) would necessarily follow after step (d) in the method of modified-Lin, such that the facing and pressing the second bonding surface to and against the first bonding surface occurs through the plurality of electrically-conductive nanoparticles therebetween.
In step (d), a whole portion of each of the plurality of electrically-conductive nanoparticles is intruded into the silicon layer by a metal assisted chemical etching method (solid-liquid-vapor etching, ¶0023, 0026, 0027 of Guiton).
Per claim 6, modified-Lin teaches the limitations of claim 5. According to Guiton, the particles
are made of copper (¶0029).
Per claim 7, modified-Lin teaches the limitations of claim 5. According to Guiton, it would have
been obvious as of the effective filing date of the claimed invention for a person having ordinary skill in
the art to vary the intrusion height into the silicon layer in order to determine the properties of the
silicon nanostructures (¶0040).
According to Guiton, the electrically conductive nanoparticles are formed at the end of the
silicon nanostructures. According to Lin, it would have been obvious as of the effective filing date of the
claimed invention for a person having ordinary skill in the art to adjust the degree of exposure of the
silicon nanostructures by varying a pressing force in order to make sure the nanostructures are
structurally supported and adhered (¶0038-0040).
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to
discover the optimum or workable ranges by routine experimentation." See In re Aller, 220 F.2d 454,
456, 105 USPQ 233, 235 (CCPA 1955). The discovery of an optimum value of a known result effective
variable, without producing any new or unexpected results, is within the ambit of a person of ordinary
skill in the art. See In re Boesch, 205 USPQ 215 (CCPA 1980) (see MPEP § 2144.05, II.).
As such, the exposure height of the plurality of electrically-conductive nanoparticles is an
obvious result of the optimization of adherence and structural support of the silicon nanostructures.
Per claim 8, modified-Lin teaches the limitations of claim 5. A semiconductor material made of
crystalline silicon or amorphous silicon is used as the silicon layer of the first semiconductor element
(¶0028 of Lin, 10023 of Guiton). The second semiconductor element is made of an organic-based
material (PEDOT:PSS, see cited passages above).
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive. Applicant argues that Guiton does not teach “intruding a portion of each of the plurality of electrically-conductive nanoparticles into the silicon layer”, on the grounds that all of each of the nanoparticles are intruded into the silicon layer. However, the claim language does not exclude a whole portion of each of the plurality of electrically conductive nanoparticles being intruded. Therefore the rejection of claims 5-8 as prima facie obvious over Lin in view of Guiton detailed above is proper.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan S Cannon whose telephone number is (571)270-7186. The examiner can normally be reached M-F, 8:30am-5:30pm PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Barton can be reached at (571) 272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Ryan S. Cannon
Primary Examiner
Art Unit 1726
/RYAN S CANNON/Primary Examiner, Art Unit 1726
Prosecution Insights