DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same
under either status.
Response to Arguments
Applicant's arguments filed 05/19/2026 regarding the prior art rejections of Claims 1 - 10 have been fully considered, and is persuasive. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.
The Remarks argue that:
Applicant asserts that the present invention is patentable over the cited art and respectfully requests allowance of claim 1. Further, Applicant asserts that both claims 9 and 10 are also patentable over Li in view of Sugioka at least due to the similar reasons.
Claim 1 recites, in part, the method is suitable for "wireless communication" and "determining a target decoding result from the plurality of decoding results of the plurality of decoders by a MUX coupled to the plurality of decoders". Li in view of Sugioka fails to disclose these limitations.
The applicant respectfully submits that neither Li nor Sugioka teaches to "determine a target decoding result from the plurality of decoding results of the plurality of decoders by a MUX coupled to the plurality of decoders".
The Examiner agrees Li in view of Sugioka fails to teach all the claim limitations of amended claim 1. However, with the addition of prior art Shaver (US 2013/0044655 A1), one skilled in the art could combine the prior arts to conclude the limitations of the amended claim. Shaver teaches a wireless communications device which may further comprise a multiplexer coupled to the decoder and configured to multiplex the first signal and the plurality of second signals. (0011) Shaver cures the deficiencies of Li in view of Sugioka, maintain the prior art rejection.
Claims 2 – 7 which depend from amended claim 1, have been considered and rejected.
Claims 11 - 15 which depend from amended claim 9, have been considered and rejected.
Claim 16 - 21 which depends from claim 10, has been considered and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20080244359 A1) in view of Sugioka (US 20230308210 A1) in view of Shaver (US 2013/0044655 A1). Claim 8 has been canceled.
In regards to claim 1, Li teaches:
A decoding processing method, comprising: performing an iterative decoding on input data by a plurality of decoders connected in successive stages (0039, FIG. 3 illustrates a second example of an iterative error correction decoder, according to another embodiment of the present invention. MF block 302 receives equalized samples from an input equalizer (not shown), as with the previous embodiment. The decoder of FIG. 3 performs an N number of decoding iterations on the equalized samples. N can be any suitable positive integer number greater than 1. Iterations 1, 2, 3, and N are shown in FIG. 3, as an example.)
Li fails to teach:
to obtain a plurality of decoding results of the plurality of decoders; determining a target decoding result from the plurality of decoding results of the plurality of decoders and outputting the target decoding result.
However, Sugioka teaches:
to obtain a plurality of decoding results of the plurality of decoders; (0247, only one decoder is illustrated on the side of the decoder 12; however, a plurality of the decoders 12 may be provided) determining a target decoding result from the plurality of decoding results of the plurality of decoders; and outputting the target decoding result (0427, the set 1, as a target, the header error correction part 232 selects information indicating successful decoding as the decoding result, and also infers that the header information of the set 1 is correct to select the header information of the set 1 as the output information.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of correcting errors using iterative decoding of Li with the teaching of Sugioka, which teaches a decoding device and method in order to improve data transmission efficiency between chips. (Sugioka: 0007, decoding in which a running disparity and a run length are controlled, without deteriorating transmission efficiency;)
Li in view of Sugioka fails to teach:
for wireless communication; by a MUX coupled to the plurality of decoders;
However, Shaver teaches:
for wireless communication; by a MUX coupled to the plurality of decoders; (0011, the wireless communications device may further comprise a multiplexer coupled to the decoder and configured to multiplex the first signal and the plurality of second signals. The decoder may comprise an iterative decoder, and the multiplexer may be configured to further multiplex extrinsic decoder data.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of correcting errors using iterative decoding of Li with the teaching of Shaver, which teaches a wireless communications device includes a receiver, and a decoder coupled downstream from the receiver in order to improve mobile communications. (Sugioka: 0002, The transceiver and the antenna cooperate to transmit and receive communications signals.)
In regards to claim 2, Li in view of Sugioka in view of Shaver teaches:
The method of claim 1, wherein performing an iterative decoding on input data by a plurality of decoders connected in successive stages to obtain a plurality of decoding results of the plurality of decoders comprises: performing the following steps for each of the plurality of decoders to iteratively decode the input data to obtain the plurality of decoding results of the plurality of decoders: picking target data from the input data and data decoded in the last iteration, wherein the number of iterations i is greater than or equal to 1, and in response to i being equal to 1, the target data is the input data; performing decoding on the target data to obtain decoded data (0089, The decoder of FIG. 7 performs a 1 to N number of decoding iterations on the equalized samples.); performing a hard decision on the decoded data; in response to the hard decision being successful, determining that the decoding is successful, and determining the decoded data as the decoding result; in response to the hard decision failing, determining the decoded data as data obtained after the current iterative decoding; and updating i to be i+1 until i reaches a preset maximum number of iterations, and then determining the decoded data as the decoding result. (0096, Hard decision decoder 716 performs hard decision decoding on the output stream of post processor 712 using any suitable hard decision-decoding scheme that has a low complexity to generate a decoded output stream. The stop condition (S<TH) in stop block 718 determines which block the decoded output stream of hard decision decoder 716 is transmitted to. At stop block 718, if the stop condition S<TH is satisfied, the decoded output stream from hard decision decoder 716 is transmitted directly to buffer block 756 (via A in FIG. 7) and then to Reed-Solomon decoder 754)
In regards to claim 3, Li in view of Sugioka in view of Shaver teaches the method of claim 2.
Li fails to teach:
wherein performing a hard decision on the decoded data comprises: determining whether a bit error is in the decoded data; in response to a determination result indicating a bit error, the hard decision fails; and in response to a determination result indicating no bit error, the hard decision is successful.
However, Sugioka teaches:
wherein performing a hard decision on the decoded data comprises: determining whether a bit error is in the decoded data; in response to a determination result indicating a bit error, the hard decision fails; and in response to a determination result indicating no bit error, the hard decision is successful. (0645, As illustrated in FIG. 53, it is assumed that a one-bit error occurs in the control code. The code illustrated on upper side of FIG. 53 is Pad Code in the inversion encoding illustrated in FIG. 46, and a code is illustrated in which a flag of one is added to one bit of the head of the Pad Code. In a case of being encoded and transmitted to the decoding side in a state where no error occurs, the code illustrated on the upper side of FIG. 53 is transmitted and received.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of correcting errors using iterative decoding of Li with the teaching of Sugioka, which teaches a decoding device and method in order to improve data transmission efficiency between chips. (Sugioka: 0007, decoding in which a running disparity and a run length are controlled, without deteriorating transmission efficiency;)
In regards to claim 4, Li in view of Sugioka in view of Shaver teaches:
The method of claim 2, wherein performing decoding on the target data to obtain decoded data comprises: performing a cyclic shift processing on the target data to obtain processed target data; performing a subtraction operation between the processed target data and an input check matrix to obtain an operation result, wherein the check matrix shares identical dimensions with the target data; picking a minimum value and a second minimum value from the operation result; updating the check matrix according to the minimum value and the second minimum value to obtain an updated check matrix; and performing an addition operation between the operation result and the updated check matrix, and then performing a cyclic reverse shift to obtain the decoded data. (0027, Minimum sum decoder 214 applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate more reliable updated soft information using the soft information generated by soft post processor 212. Minimum sum decoder 214 then computes the difference between the updated soft information and the soft information generated by soft post processor 212 to generate extrinsic information. The extrinsic information from minimum sum decoder 214 (and from the other minimum sum decoders described herein) is the difference in the metric between the updated soft information and the soft information generated by soft post processor 212.)
In regards to claim 5, Li in view of Sugioka in view of Shaver teaches the method of claim 1.
Li fails to teach:
wherein before performing an iterative decoding on input data by a plurality of decoders connected in successive stages to obtain decoding results of the plurality of decoders, the method further comprises: acquiring a degree of parallelism of the input data and a delay requirement of received data; and determining a number of decoders according to the degree of parallelism and the delay requirement.
However, Sugioka teaches:
wherein before performing an iterative decoding on input data by a plurality of decoders connected in successive stages to obtain decoding results of the plurality of decoders, the method further comprises: acquiring a degree of parallelism of the input data and a delay requirement of received data; and determining a number of decoders according to the degree of parallelism and the delay requirement. (0438, data for one line is transmitted by the data transmission processing, the data reception processing is performed, and when the pixel data for one line is received by the data reception processing, the data transmission processing is performed on the pixel data of the next one line, as a target. The data transmission processing by the transmission unit 122 and the data reception processing by the reception unit 131 may be appropriately performed temporally in parallel, in some cases.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of correcting errors using iterative decoding of Li with the teaching of Sugioka, which teaches a decoding device and method in order to improve data transmission efficiency between chips. (Sugioka: 0007, decoding in which a running disparity and a run length are controlled, without deteriorating transmission efficiency;)
In regards to claim 6, Li in view of Sugioka in view of Shaver teaches:
The method of claim 1, further comprising: in response to the input data being code block data, determining a number of code block data input to each decoder according to a low-density parity check code (LDPC) code block length, wherein the number of code block data is a ratio of the LDPC code block length to the number of decoders. (0005, A low density parity check (LDPC) code is a linear error-correcting code that has a parity check matrix H with a small number of nonzero elements in each row and column. LDPC codewords can be decoded using soft-decision decoding. LDPC codes can be defined over any finite field. For example, an LDPC codes can be defined over a Galois field GF(2), in which "1" is the only nonzero element. The row (or column) weight (or degree) of an LDPC code refers to the number of elements that have a non-zero value among the numbers in rows (or columns) of the parity check matrix.)
In regards to claim 7, Li in view of Sugioka in view of Shaver teaches:
The method of claim 6, wherein performing an iterative decoding on input data by a plurality of decoders connected in successive stages comprises: activating a first decoder to cause the first decoder to enter a decoding state, and in response to an m-th code block data being input, performing the iterative decoding on the m-th code block data by the first decoder, and recording a state of the iterative decoding by head which is m-1, and tail which is 0, wherein m is greater than or equal to 1 and less than or equal to a number x of code block data input to the decoder, head indicates a serial number of the input code block data, and tail indicates a number of rounds of decoding performed in parallel by the plurality of decoders; activating a j-th decoder to cause the j-th decoder to enter the decoding state, and in response to an m+(j-1)x-th code block data being input, performing the iterative decoding on the m+(j-1)x-th code block data by the j-th decoder, and recording a state of the iterative decoding by head and tail, wherein head is m+(j-1)x-1, tail is 0, and j is greater than 1 and less than or equal to the number of decoders; and after all of the plurality of decoders enter the decoding state, performing the iterative decoding on the input code block data in parallel by the plurality of decoders. (0095 & CLAIM 23, The minimum sum decoders used in the decoder of FIG. 7 have a low level of complexity, cause less error propagation, and have a more controllable error floor, because they use LDPC codes that have low weights, and because they use a small number (e.g., one or 2) of local iterations. the iterative decoder stops performing iterations if early stop parameters generated by the first decoder are less than a threshold value, and the decoded output stream of the hard decision decoder is transmitted to the second post processing block only if the early stop parameters are greater than or equal to the threshold value.)
With regards to claim 9, Li teaches:
A non-transitory computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform a decoding processing method (0039, FIG. 3 illustrates a second example of an iterative error correction decoder, according to another embodiment of the present invention. MF block 302 receives equalized samples from an input equalizer (not shown), as with the previous embodiment. The decoder of FIG. 3 performs an N number of decoding iterations on the equalized samples. N can be any suitable positive integer number greater than 1. Iterations 1, 2, 3, and N are shown in FIG. 3, as an example.)
Li fails to teach:
to obtain a plurality of decoding results of the plurality of decoders; determining a target decoding result from the plurality of decoding results of the plurality of decoders and outputting the target decoding result.
However, Sugioka teaches:
to obtain a plurality of decoding results of the plurality of decoders; (0247, only one decoder is illustrated on the side of the decoder 12; however, a plurality of the decoders 12 may be provided) determining a target decoding result from the plurality of decoding results of the plurality of decoders; and outputting the target decoding result (0427, the set 1, as a target, the header error correction part 232 selects information indicating successful decoding as the decoding result, and also infers that the header information of the set 1 is correct to select the header information of the set 1 as the output information.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of correcting errors using iterative decoding of Li with the teaching of Sugioka, which teaches a decoding device and method in order to improve data transmission efficiency between chips. (Sugioka: 0007, decoding in which a running disparity and a run length are controlled, without deteriorating transmission efficiency;)
Li in view of Sugioka fails to teach:
for wireless communication comprising: performing an iterative decoding on input data by a plurality of decoders connected in successive stages; by a MUX coupled to the plurality of decoders;
However, Shaver teaches:
for wireless communication comprising: performing an iterative decoding on input data by a plurality of decoders connected in successive stages; by a MUX coupled to the plurality of decoders; (0011, the wireless communications device may further comprise a multiplexer coupled to the decoder and configured to multiplex the first signal and the plurality of second signals. The decoder may comprise an iterative decoder, and the multiplexer may be configured to further multiplex extrinsic decoder data.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of correcting errors using iterative decoding of Li with the teaching of Shaver, which teaches a wireless communications device includes a receiver, and a decoder coupled downstream from the receiver in order to improve mobile communications. (Sugioka: 0002, The transceiver and the antenna cooperate to transmit and receive communications signals.)
With regards to claim 10, Li in view of Sugioka in view of Shaver teaches the electronic device and corresponds to claim 9 as analyzed accordingly.
With regards to claim 11, Li in view of Sugioka in view of Shaver teaches non-transitory computer-readable storage medium of claim 9, and corresponds to claim 2 as analyzed accordingly.
With regards to claim 12, Li in view of Sugioka in view of Shaver teaches non-transitory computer-readable storage medium of claim 11, and corresponds to claim 3 as analyzed accordingly.
With regards to claim 13, Li in view of Sugioka in view of Shaver teaches non-transitory computer-readable storage medium of claim 11, and corresponds to claim 4 as analyzed accordingly.
With regards to claim 14, Li in view of Sugioka in view of Shaver teaches non-transitory computer-readable storage medium of claim 11, and corresponds to claim 5 as analyzed accordingly.
With regards to claim 15, Li in view of Sugioka in view of Shaver teaches non-transitory computer-readable storage medium of claim 9, and corresponds to claim 6 as analyzed accordingly.
With regards to claim 16, Li in view of Sugioka in view of Shaver teaches electronic device of claim 10, and corresponds to claim 2 as analyzed accordingly.
With regards to claim 17, Li in view of Sugioka in view of Shaver teaches electronic device of claim 16, and corresponds to claim 3 as analyzed accordingly.
With regards to claim 18, Li in view of Sugioka in view of Shaver teaches electronic device of claim 16, and corresponds to claim 4 as analyzed accordingly.
With regards to claim 19, Li in view of Sugioka in view of Shaver teaches electronic device of claim 10, and corresponds to claim 5 as analyzed accordingly.
With regards to claim 20, Li in view of Sugioka in view of Shaver teaches electronic device of claim 10, and corresponds to claim 6 as analyzed accordingly.
With regards to claim 21, Li in view of Sugioka in view of Shaver teaches electronic device of claim 20, and corresponds to claim 7 as analyzed accordingly.
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Murakami (US 2013/0322566 A1): Disclosed is a precoding method for generating, from a plurality of baseband signals, a plurality of precoded signals that are transmitted in the same frequency bandwidth at the same time. According to the precoding method, one matrix is selected from among matrices defining a precoding process that is performed on the plurality of baseband signals by hopping between the matrices. A first baseband signal and a second baseband signal relating to a first coded block and a second coded block generated by using a predetermined error correction block coding scheme satisfy a given condition.
• Rault (US 2012/0036410 A1): A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include progressively enabling and disabling nodes of the iterative decoder to perform iterative decoding on a demodulated signal to provide a decoded signal with minimal variation of a supply voltage.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office
action. Applicant's arguments filed 05/19/2026 regarding the prior art rejections of Claims 1 – 10 have
been fully considered and are persuasive.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 7/24/2026
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